Buffered SPI communication

[soumen21]

I have a Master and a SPI slave device. On the master end I have FPGA and buffers and on slave side buffers and Processor. Arrangement shown below

The above works fine for distance of the slave device from the controller up to 22 feet. The devices are placed on a carrier board. Processor on the slave is MC68HC705C9A (5V operated)


In the new arrangement (shown below), for a required change, the processor is replaced with SPARTAN 3 FPGA and level translators are used to make the signals compatible to 3.3V of the FPGA.

With the new arrangement with FPGA and voltage translators, the master sometime reports IO device communication error when the device is below 16ft from the MASTER.
And when the distance from the Master to slave is more than 16 feet, the the MASTER always reports IO device communication error.

What could be the probable issue?

Regards
Soumen

 

[KlausST]

Hi,

Missing informations:
* SCK frequency
* wiring, type, characteristic impedance
* if used: termination resistor value
* if used: series resistor value
* scope picture of the signal at the receiver side

Fail is quite expectable.
Single ended signals (combined with not impedance controlled wiring) are not useful for long distance. Buffered or not will not make much difference.
--> Use differental signaling and impedance controlled twisted pair lines.
RS422 or LVDS.

If you insist on single ended wiring, then you need some series resistors to reduce ringing (echo), maybe some kind of termination will help. Next step is to reduce SCK frequency.

Klaus

 

[soumen21]

Thanks Klaus for the reply.
The Clock at the device side is 1 MHZ and at the MASTER is 500 KHz (NOT Gate at master end)
Series termination of 18R is used for the clock. For wiring twisted pair is used.

The setup works fine with the processor board but fails with the FPGA board for longer distances.
I have attached few waveforms for reference.

 

[FvM]

Technically it's no problem to get single ended SPI transmission over 20 ft and more with proper line termination, e.g
source side series termination. For higher speeds, cable propagation delay must be taken into consideration. Common mode noise involved with longer transmission distance suggest to use differential signalling however.

--- Updated Mar 29, 2021 ---

Not sure how you connect twisted pair with single ended signals. 18 ohms seems far too low. Will have a look at the waveforms.

 

[KlausST]

Hi,

The Clock at the device side is 1 MHZ and at the MASTER is 500 KHz (NOT Gate at master end)

I don't know how this can work. SPI is sychronous transfer with surely identical bit rate on master and slave.
A NOT gate does not change frequency nor bit rate.

Klaus

 

[soumen21]

Sorry my apologies, at the MASTER input we have 47 Ohms and 470 pF before the NOT gate.

At the device side it is as shown below

 

[KlausST]

Hi,

orry my apologies, at the MASTER input we have 47 Ohms and 470 pF before the NOT gate.

Confusing.
Is the long wiring on the right side or left side?
From the signal flow it should be
MASTER_out -> series R -> long wires -> RC -> schmitt_trigger -> SLAVE_in

Please keep on schematic standard signal flow from left to right.

Klaus

 

[Aussie Susan]

If you are already changing the hardware, why not use a hardware protocol that is designed for long distance communication. (That does not mean you need to change the higher level protocols but that might enhance communication reliability as well.)
Susan