buffer for digital signals

[fady232]

Hello all, i was simulating a buffer for digital signals , and i had some questions, if someone could help, thanks.

First of all the first stage made of npn basically does this: I got a pulse wave that goes from 0 to 5V as VIN, and as output i got the same wave but with a drop of 0.7V ( so from 0-4.3V, for now the output doesnt see the capacitive load, so everything is fine, beside that i got this voltage drop)

Now lets pass to second stage: in the second stage im giving a square wave that goes from 0 to 4.3V , what the pnp does? he shifts the wave up by 0.7

so what im gonna see is a wave that goes from 0.7 to 5V, now my question is: is this way correct to analyze circuit? im looking at right things? am i missing something?

Second question: why does the simulation dont show the distortion in the second stage vout? the stage with the capacitor?, when pulse wave goes low from 5V-->0V the voltage drops and the 100pF discharges via the 10k resistor with a tau given by tau=R*C, but in that way i shouldnt see a perfect square wave, cus it goes ''slowly'' to 0V or im wrong?


Thanks for whoever gonna answer and sorry if im a bit newbie, but trying to learn as much as i can

 

[KlausST]

Hi,

do the calculation: what is your tau ... in numbers?
Then decide how it matches your picture.

*****

You say "buffer" .. but what does it (or is it supposed to) buffer? Voltage, current, timing, something else?

Klaus

 

[fady232]

Hi,

do the calculation: what is your tau ... in numbers?
Then decide how it matches your picture.

*****

You say "buffer" .. but what does it (or is it supposed to) buffer? Voltage, current, timing, something else?

Klaus

buffer to voltage

 

[KlausST]

If you want to buffer the voltage .. but the output voltage is less than before then you´re doing something wrong.

Klaus

 

[fady232]

If you want to buffer the voltage .. but the output voltage is less than before then you´re doing something wrong.

Klaus

i know this isnt ideal circuit, im trying to simulate it tho and understand why things happen in this circuit

 

[dick_freebird]

Why are you using discrete bipolars to buffer
CMOS logic signals? A pair o CMOS inverters
will be faster, use less DC power and not lose
output swing.

 

[fady232]

Why are you using discrete bipolars to buffer
CMOS logic signals? A pair o CMOS inverters
will be faster, use less DC power and not lose
output swing.

Ye i know cmos inverter is a common way, where did u learn that tho if i can ask?

 

[emmamia12]

Stage 1 (NPN Emitter Follower):
Yes, output = input – VBE ≈ 0.7V drop. So VIN 0–5V gives VOUT1 ≈ 0–4.3V. This stage buffers with high input, low output impedance.

Stage 2 (PNP Emitter Follower + Cap Load):
VOUT2 ≈ VOUT1 + 0.7V ⇒ 0.7–5V swing. The capacitor (100pF) + 10kΩ forms an RC filter:
τ = RC = 1μs → fall time ~5μs, so you should see rounding on falling edges.

No Distortion?
Probably your sim’s timestep is too large, or waveform edges aren’t sharp enough.

Try This:
Add .OPTIONS MAXSTEP=100n or zoom in on edges (~4s, 8s) to see the curve.

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Let me know if you want to clean it up even more!