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Currently I am running the simulation for Buck converter.
I need to run with process variation (High Vth MOS corner, Low Vith MOS corner, High resistance reisitor corner, Low resistance resistor corner), temperature variation and Input voltage variation to make sure all simulation items in specification.
The simulation items consists of Efficiency, Load Regulation, Line Regulation etc.
It is very time consuming to run simulation through all combination. So, I am planning to select to worst case condition for each simulation items.
lowest Effiency condition: MOS vth High or Low, resistance high or low, temperature High or Low, Vin High or Low..... but I have no idea how to choose.....
If you can't predict the effect then you have to run the corners.
And the thing about DC-DCs is, there are many competing spec
dimensions, for any given corner you will likely improve some and
degrade some others.
Selecting imaginary worst cases leaves a good possibility that
you were wrong and will be surprised later. You ought to derive
your understanding from simulations during the early design
phases and note block-level corner sensitivities, and make sure
you hit the significant ones, if you want to play that kind of
game. But thoroughness is better, even if it costs you time.