Buck Converter mosfet swithces problem

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kah89

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Hi

I am designing buck converter in cadence and i have some problems with the mosfet switch when I add an ideal switches and check the switching waveform it looks ok "square wave with the desired duty cycle" but when I add the mosfets the waveform changes and I don't know why. attached the schematic and the waveform images

 

Looks like feedthrough of huge gate capacitances. Curiously the PMOS transistor doesn't seem to switch on.
 
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    kah89

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I think you need to change the load resistance value which is shown as 400 m ohm. Increase it to atleast 10k ohm and check.
 
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ravindragudi said:
I think you need to change the load resistance value which is shown as 400 m ohm. Increase it to atleast 10k ohm and check.
Click to expand...

Nothing happened.

FvM said:
Looks like feedthrough of huge gate capacitances. Curiously the PMOS transistor doesn't seem to switch on.
Click to expand...

It turns on when the gate signal is zero.
 

Looks like the PMOS transistor is slow to switch and the NMOS is not turning on.
What are the threshold voltages of the MOSFETs?
Changing the load resistor value has no effect?? It should have some effect.
 
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    kah89

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The frequency of the MOSFET switching is not clear in the graphs. Can you check this and simulate again with frequencies in the order of 100kHz. Don't forget to change the load resistance. 0.4 ohm resistor may not be good idea with given C and L values here.
 
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I found the problem, it was the on resistance of the two mosfets I didn't adjust it to a suitable value but now it is working. Thank you.

My last question is how to calculate the input power with cadence i tried (Iavg*V) but it is too large
 

My last question is how to calculate the input power with cadence i tried (Iavg*V) but it is too large
Click to expand...
Iavg*V is of course right. The question is how much power is consumed by shoot-trough, simulataneous conduction of both MOSFETs. You may want to generate separate gate signals with deadtime.
 
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Thank you, It was the overlapping clock problem
 

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