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break combinational feedback loop.

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xiongdh

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combinational feedback loop

do I need to break combinational feedback loop at all conditions? How can i break combination feedback loop.What do the command set_disable_timing do to the combinational ciucuit in DA?

thanks!!!
 

Al Farouk

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combinational feedback loops

combinational feedback should be avoided except your are intended to build a ring oscillator as it will cause one of two things
1- it will feed the sam logic: in this case it will add nothing
2- it will feed the oposit logic: the node will oscillate by time period equal to double the path delay (i.e ring osiclator will be built).

you can break it either by
1- build a clocked system by putting a DFF in the feedback path which load the value on a ckock edge.
2- make a gated feedback but you by attention for the gating signal timing with respect to system functionality

regards
 

FNK

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combinational feedback what is

How are these combinatinol loops get synthesized in the first place. What constructs are to be avoided...
 

xiongdh

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combinational feedback loop example

"""2- make a gated feedback but you by attention for the gating signal timing with respect to system functionality."""


But gated feedback can't be recognized by DC, It is still Reported that "Warning: Disabling timing arc between pins 'H01' and 'N01' on cell 'sbox/U524' to break a timing loop"

How can i deal with this? and do this timing loop affect the compile result such as the timing path calculating?
 

Al Farouk

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breaking combination loop

first of all you should try to avoid writing code that generte the combinational feedback, if it is essaintial to your design you start search for a solution for it. I did not use the DC. but if it is possible you can post ur code and explain the target idea so we can help.

regards
 

vsop

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logic loop breaking sta

Mmm...., i am not sure i'm right or not. Solving the combinational loop problem is not necessary if using vector-based simulation, but it had better be solved if adopting either STA or DFT in your flow. As to using disable timing command to break the timing loop, i never make it successfully through the whole synthesis process. Once the design is changed by DC, it seems these setting are lost. u had better call the supports from the syn@psys, u can share with us once you get the solutions.
 

Al Farouk

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timing loop + synopsys

What about the progress with you dehuixiong regarding that issue
regards
 

xiongdh

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sta & combinational loop

Thank you all.
I correct this problem by just make another copy of the combinational circuit and break the loop from verilog codes.
I find the DC calculated the timing path of a combinational circuilt loop more than one times. I want to call help from synopsys.But their help is not free.
May be set_false_path command can be useful but i don't know how to do with it.
 

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