Yes, look at the CLB guide for whatever device you have. The short explanation is that Xilinx FPGAs have SLICEL, SLICEM, and SLICEX. The SLICEM can be used as DMEM/SRL32 as well as anything in a SLICEL. THe SLICEX is only on lower end devices and has less features than a SLICEL. At least, from what I can recall.
I suspect this is 256 LUTs from SLICEM's for the ram, and 342 SLICE*'s for any clock enable and muxing.
--edit:
in general, any depth over 256 or maybe 512 is probably better done in a BRAM. This is based on the DMEM configurations. Likewise, ram configs below 32 might be better served by a DMEM of size 32. These are because a SLICEM can be a 1 bit, 256 depth RAM, or a 6 bit, 32 depth RAM. (the latter is because the SLICEM is 4 LUTs with a shared write address, but 3 independent read addresses. It also has f7/f8 muxes to allow 2-4 LUT outputs to be quickly muxed.)