I have found cool code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bram8 is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector(7 downto 0));
end bram8;
architecture behavioral of bram8 is
signal addr : std_logic_vector(11 downto 0);
type init_array_type is array(natural range <>) of std_logic_vector(7
downto 0);
constant bram8_data : init_array_type :=(
X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07" ,
X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F" ,
X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07" ,
X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F" ,
X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F" ,
X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07" ,
X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F" ,
X"00", X"FF"
);
begin
LUT_proc : process(clk)
begin
if( clk'event and clk='1') then
if(rst='1') then
q <= (others=>'0');
addr <= (others=>'0');
else
q <= bram8_data(CONV_INTEGER(addr));
addr <= addr + 1;
end if;
end if;
end process;
end behavioral;