abhisheknag
Newbie level 1
Hello,
I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.
Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?
Thanks and regards,
Abhishek
I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.
Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?
Thanks and regards,
Abhishek