[Boundary Scan] TMS width can be more than 1 bit?

[maulin sheth]

Hello All,

Suppose, I have 3 Chips on the Board.Each chip have JTAG and TAP Controller.
Now I want to know that,For On Board Testing,
1) Do we need Master TAP Controller which taking control for all 3 chips?
2) I have 3 chips on board,so does it mean that I should have 3 bits of TMS or TMS Bus of 3 bits.So I can access 3 chips parallely.
3) If I don't have 3 bits of TMS. thn the same operation can be applies to all the chips as TMS is same for all the three chips.

Thanks & Regards,

 

[FvM]

JTAG interfaces of multiple chips are can be comibined by chaining TDO to TDI. TCK and TMS are parallel connected to all chips.

I don't see a particular advantage of having multiple TMS signals compared to a usual JTAG chain. For fully indpendent access, all JTAG signals would be generated individually.

 

[maulin sheth]

JTAG interfaces of multiple chips are can be comibined by chaining TDO to TDI. TCK and TMS are parallel connected to all chips.

I don't see a particular advantage of having multiple TMS signals compared to a usual JTAG chain. For fully indpendent access, all JTAG signals would be generated individually.

Thanks.

But do we need Global/Master TAP Controller? In which application,we prefer Global/Master TAP Controller?