Boundary scan IEEE 1149 for Memory test

[sudarsv]

Hi all

I am currently designing SRAM with BIST which will run March tests to test the SRAM. I came across the IEEE 1149 standard for testing but was not able to find good documentation for memory test using IEEE 1149 standard. Here r a few quick question. Can you please help me in clarifying them

1. Can Boundary scan be used for testing SRAM.
2. Can you provide me with some good documentation where boundary scan is used for SRAM test.

Thank you

Regards
Sudarshan

 

[sudarsv]

Hi all

Can you please help me in understanding how to use boundary scan IEEE 1149.1 standard to test SRAM..

Its very urgent..... please help me

 

[pavanhs]

Hi all

Can you please help me in understanding how to use boundary scan IEEE 1149.1 standard to test SRAM..

Its very urgent..... please help me

Since SRAM is an memory you can't test with only Boundary Scan IEEE1149.1
But in Cadence Encounter you have to insert Boundary Scan and Memory Bist at a time.
Because from Boundary scan ports we have to give input and read back the results.

So Boundary Scan is not only essential for testing SRAM


---
Pavan HS

 

[ljwfred]

do you mean that you are coding a kind of mbist which uses the BSD to test the memories?

it sounds familiar,
some kind of tools can generate this kind of verilog, like mentor tessent

but it uses jtag IRs to shift in some instructions and shift out some results.
i think it is.