Boundary scan functionality of JTAG for onboard Flash programming

[tramu]

Dear Sir,

I would like to know whether we can use Boundary scan functionality of JTAG for programming onboard Flash device without initializing core CPU/processor (JTAG compliant Processor).

During initial board bring up, we need to program the onboard empty flash using JTAG interface.
But, we don't want to use processor core logic for programming Flash as after initial assembly, we will not be sure of correct working of it.

So, is it possible to program onboard (boot & Code) flash(NAND/NOR/SPI) using the JTAG interface on the processor, without initializing processor core logic.

Thanks,
Thulasi

 

[FvM]

It's possible for most procesors and supported by a number of commercial and open source JTAG tools. By nature (the full JTAG chain length must be shifted for each state change of any processor pin) it's rather slow, so it may be effectively useless for production purposes when dealing with large memory capacities.

E.g. https://www.xjtag.com/

 

[psatish1264]

Hi,

https://www.abielectronics.co.uk/Products/jtag.php

 

[Barry Pearson]

Hi Thulasi

Indeed this is a technique that is used regularly in board bring-up and also in manufacturing.

For board bring-up you have a choice of the slower tools that can be used (jtaglive, xjtag, abi etc..)
and of these jtaglive 'script' is probably the cheapest/best value and easiest to get started with as it uses standard Python coding.

Pay more money and you can get fast controllers that will cope with production programming requirements
e.g. JTAG Technologies DataBlaster series. It may also depend on where you are
based as to who can offer the best support.

Let us know how you get on.

Barry

 

[FvM]

Pay more money and you can get fast controllers that will cope with production programming requirements
e.g. JTAG Technologies DataBlaster series.

Yes, there are performance differences. Programming SPI flash as mentioned in the initial post through generic boundary scan will be very time consuming, even with fastest available TCK rates.

 

[Barry Pearson]

Yes, there are performance differences. Programming SPI flash as mentioned in the initial post through generic boundary scan will be very time consuming, even with fastest available TCK rates.

Agreed, although parallel flash times (NOR/NAND) can still be acceptable. Moreover, when programming via an FPGA it can be possible
to create a short 'pseudo' boundary-scan register within the gate array which can be accessed/controlled by FPGA user codes. This is essentially what is happening when Altera is using it's Active Serial mode. Of course this may not help Thulasi, but we don't (yet) have the full details of the design.

Cheers

BP

 

[tramu]

Thanks a lot for your replies.

Is it possible to program NAND flash using a JTAG compliant processor using boundary scan functionality of JTAG. If so, please elaborate the procedure.

**broken link removed** can do NOR flash programming using boundary scan functionality.

 

[FvM]

Is it possible to program NAND flash using a JTAG compliant processor using boundary scan functionality of JTAG.

It's technically possible, but I don't know if it's supported by an existing JTAG tool without additional script programing.

NAND flash is rarely used as primary boot medium, because it needs an additional software layer to guarantee data integrity.

 

[tramu]

Hi,

Thanks for your reply.

I would like to confirm if the minimum flash programming time is calculated by the following equation,

{(#bits in chain) * (#scans/write) * (#writes/location) * (#locations)} / TCK frequency.

If so, please explain how the respective terms in the above equation be calculated for a given JTAG compliant CPU and NOR flash device.

Regards,
Thulasi

 

[Barry Pearson]

Hi,

Thanks for your reply.

I would like to confirm if the minimum flash programming time is calculated by the following equation,

{(#bits in chain) * (#scans/write) * (#writes/location) * (#locations)} / TCK frequency.

If so, please explain how the respective terms in the above equation be calculated for a given JTAG compliant CPU and NOR flash device.

Regards,
Thulasi

HI Thulasi

I thought I had replied to your thread but I ended up making 2 new ones . If you look around you can see my strange random postings on NAND Flash and Flash Programming rate.

BP

 

[FvM]

Perhaps a moderator can move the helpful posts to this thread.

https://www.edaboard.com/threads/258268/
https://www.edaboard.com/threads/258255/

 

[tramu]

Hi,

Also my observation is that, boundary scan flash programming requires that the FLASH memory’s address, data and control signals be directly connected to an 1149.1 compliant device so that device’s boundary register can be scanned during each FLASH write sequence.

Is my observation correct ?

Is it possible to program flash device if the address and data lines coming from the JTAG compliant device(Processor) are multiplexed using a latch enable signal from the processor ?

 

[FvM]

Is it possible to program flash device if the address and data lines coming from the JTAG compliant device(Processor) are multiplexed using a latch enable signal from the processor ?

Why not?

But it makes programming even more time consuming and possibly isn't supported by existing JTAG flash tools, needing specific scripting.