boundary scan: all outputs detected as "1"

[buenos]

topjtag

hi

I am trying to debug my board+FPGA code with an Actel ProASIC3 FPGA.
I am using urjtag test program, send out the sample/preload instruction, then scan pin states. It seems that it scans the input signals correctly, but for all outputs it says signal state = "1".

why is it?
how can I scan if the FPGA sets the output signals correctly WITH JTAG BSCAN?

 

[Joe Black]

boundary scan & output input

You can try to watch pin states with another boundary-scan tool -- TopJTAG Probe **broken link removed**. It's a GUI software and therefore more easier to use then urjtag.

If you still have a problem, please, share a link to your FPGA BSDL file. So we can see what kind of boundary-scan cells are attached to FPGA pins.

 

[buenos]

how to edit bsdl file

hi

this topjtag looks good, i will try it tomorrow. looks similar to the universalscan that we purchased in my previous job for 1000$. (that was very cool)

here is my bsdl file:
**broken link removed**
i was wondering if this problem is normal when doing sample/preload, or it is related to the chip used...

 

[Joe Black]

boundary scan cell in fpga

I found the answer inside the BSDL file:

-- This BSDL file reflects the pre-programming JTAG
-- behavior. To reflect the post-programming JTAG
-- behavior, edit this file as described below:

-- If the I/O is unused or configured as an output,
-- the input boundary scan cell becomes internal only.
-- The input buffer is turned off, and you can not
-- transfer data from the I/O pad into the input scan
-- cell. For example:
-- IO(1) is an output, the BSDL entry would be modified
-- from:
-- " 0 (BC_1, IO(1), input, X), "&
-- " 1 (BC_1, IO(1), output3, X, 2, 0, Z), "&
-- " 2 (BC_1, *, control, 0), "&
-- to:
-- " 0 (BC_1, *, internal, X), "&
-- " 1 (BC_1, IO(1), output3, X, 2, 0, Z), "&
-- " 2 (BC_1, *, control, 0), "&
-- No modification is necessary when the I/O is
-- configured as an input.

 

[buenos]

how to read pin states using urjtag

thanks.
and what is "" 0 (BC_1, IO(1), input, X), "& " ?

 

[Joe Black]

actel post program bsdl

and what is "" 0 (BC_1, IO(1), input, X), "& " ?

* It is not my text, I've just copy-pasted a comment from the BSDL file which answers your original question. This line was a part of that comment in the BSDL file.

* Just decided to add some more explanation:
Usually a bidirectional pin has 3 boundary-scan cells associated with it. Input cell catches the real signal value on a pin, control cell shows if output is disabled or not, output cell (when control is enabled) shows what pin is trying to output.

But in this particular device, a bidirectional pin when configured as output, has only 2 boundary-scan cells: control and output. There is no possibility to see a real signal value on such a pin, it is only possible to see what value a pin is trying to output.

 

[buenos]

sample only boundary scan cells

for example when I know that the code is driving a signal low and measure it by scope/multimeter, the jtag program shows high.
is it possible that the program checks the control cell instead of the output cell? (bug)

 

[Joe Black]

sample only bounday scan cell

for example when I know that the code is driving a signal low and measure it by scope/multimeter, the jtag program shows high.
is it possible that the program checks the control cell instead of the output cell? (bug)

There is no bug in urjtag or TopJTAG Probe. The problem is the BSDL only valid for a pre-configured device and must be modified to used with a configured device. On a pre-configured device each bidirectional pin has 3 associated boundary-scan cells (input, control and output). When device is configured, boundary-scan logic is also slightly modified. Output pins now only have 2 associated boundary-scan cells (control and output). Input cells for these output pins are still present in boundary-scan register but are no longer connected to pads and contain garbage. However, the original BSDL file tells urjtag or TopJTAG Probe that output pins still have 3 cells and that is why both urjtag and TopJTAG Probe read a garbage from input cells and return it as a pin state.

You should use a modified BSDL file for a configured device. Xilinx has BSDLAnno and Altera has BSDLCustomizer tools to generate BSDL file for configured devices. Probably, Actel has a similar tool.

I found a little info on how to generate a device-specific BSDL file. From **broken link removed**

Actel BSDL Files
Actel BSDL files are grouped into two categories: generic and device-specific. Generic files are available
for all product families on the web at http://www.actel.com/download/bsdl/default.aspx. The generic files
assign all user I/Os as inout. Generic BSDL files can also be generated for most product families in Designer
software using File > Export > Auxiliary Files. Device-specific files assign user I/Os as input, output, or
inout. However, note that device-specific files still use generic names for user I/Os (e.g., IO_19).
The choice of a generic or device-specific file is controlled by the GENERICBSDL variable in the Designer
software. This is set or changed via Options > Set Variable. A value of '1' indicates a generic file,
whereas a '0' value will generate a device-specific file.

If you can't generate a modified BSDL file you still can use the original file with TopJTAG Probe this way:
In TopJTAG Probe a pin value is displayed as a input/output pair (value from input cell/value from control and output cell). Simply ignore the input value before slash and see on an output value after slash. Also TopJTAG Probe allows to choose how pins are displayed on package view: select menu "View -> Inout Pins Displaying -> OUT of inout" to display values from output and control cells.

 

[buenos]

actel boundary scan cell

thanks.
i will try these.

today i used the generated bsdl file but still wrong. as you said, "GENERICBSDL variable in the Designer " should fix it too.

topjtag was not working for me, it said no parallel ports found. i have a pcmcia parallel port, the xilinx, the urjtag and the universalscan can find it fine.