[SOLVED] Bootstrapped switch

[theguardian2001]

Hi everyone! I am currently trying to test a bootstrapped switch for a further usage in S/H circuit. I have successfully tested it, but noticed that the switch behaves it worse closer to positive supply rail (see the attachments). I was wondering if there is anybody who can explain to me, why the signal sampled on the capacitor, i.e. Vgate, deviates so much from the input waveform as it gets closer to VDD?
P.S. The switch configuration is very close to the one discussed before on the forum https://www.edaboard.com/threads/sampling-switch-uses-a-bootstrapping-technique.404818/ . The circuit diagram is better seen in this thread.
Thanks everyone in advance.

 

[sidun.av]

Check the Vgs of the main switch - probably it's not enough to keep the transistor properly opened (when your source terminal is nearly at VDD). This may be caused by the capacitor being too small or the device that charges the capacitor being too narrow.

 

[abab1394]

The body of M3 not right, PMOS body should fix at the highest voltage.

 

[theguardian2001]

The body of M3 not right, PMOS body should fix at the highest voltage.

Hi abab1394, thank you for your comment. You are right that body of M3 should be at the highest voltage, but I would like this body potential to stay constant, ie keeping it on dc. If I actually connect it to the gate of the main switch, it will vary which will make it more challenging for me as a designer to predict a behavior.

--- Updated Feb 15, 2025 ---

Check the Vgs of the main switch - probably it's not enough to keep the transistor properly opened (when your source terminal is nearly at VDD). This may be caused by the capacitor being too small or the device that charges the capacitor being too narrow.

Hi, sidun.av! I really appreciate your reply - it has helped a lot in investigating a reason for my issue. After increasing the cap size and the width of those transistors which charge the cap - the resolution increases, but not significantly. However, the answer has appeared to be pretty obvious - the width of the main switch is too small. Looking at these long transients of the top plate of the sampling capacitor I suggested that R_on is too large. I guess increasing the width contributes both from decreasing R_on perspective and from the point you have mentioned in your post - the gate voltage of this switch.
The gate capacitance will also increase, but I guess that scaling the width from 1 to 3 should not be critical. I have also tried to increase the bootstrapping cap and its' switches up to some ridiculously high values - but, as I have mentioned, contributions from these factors is negligible compared to width of the "core"-switch.

 

[sidun.av]

@theguardian2001 , very good, I am glad that it helped!