Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Bootstrapped switch Sample and Hold circuit - with dummy and without dummy

Status
Not open for further replies.

wandola

Junior Member level 3
Joined
Jul 20, 2005
Messages
31
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,554
Dear all,

I am designing a low-to-medium S/H circuit for an ADC. The sampling switch is a bootstrapped switch to linearize the on-resistance.

I first designed a bootstrapped switch, and I simulated the waveforms and obtained DFT and THD in cadence with the calculator.

After that, I also designed a dummy switch to cancel the charge-injection and clock feedthrough. I think the results is not bad.

I also obtained the new output DFT and THD. However, I found the DFT plot of the S/H output with and without dummy is almost the same. ( the 2nd harmonic, 3rd harmonic, magnituedes are almost the same)

But from the transient simulation results I can see the S/H with dummy actually has betteer accuracy.

Can anyone command on this?



You can see the three lines for Vin, Vout_no_dummy and Vout_withdummy, respectively.
 

I also attached the two DFT plot here.

It can be seen that the 2nd harmonic distortion for S/H with dummy is actually 1dB worse than without dummy.

Is it possbile that the DFT plot is not correct?

I did DFT with coherent sampling. Please take a look
 

Attachments

  • withoutdummy.png
    withoutdummy.png
    3.8 KB · Views: 134
  • withdummy.png
    withdummy.png
    3.8 KB · Views: 108

In a first order, charge injection causes a fixed (or linearly voltage dependant) offset but only few non-linearity. Thus it doesn't show up in DFT. Adding the compensation FET can even add some non-linearity, as your measurement shows. Not surprizing in my opinion.
 
In a first order, charge injection causes a fixed (or linearly voltage dependant) offset but only few non-linearity. Thus it doesn't show up in DFT. Adding the compensation FET can even add some non-linearity, as your measurement shows. Not surprizing in my opinion.



Thanks a lot man. I understand now.

That really helps.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top