Bootstrap Capacitor design for low frequency

[abhikuvar]

I am trying to design a gate driver for low frequency (60 Hz) H-bridge application. I am using AdUM 3223 by ADI as gate driver for this particular application. Can anyone here please advise what precautions should be taken while finding out values for bootstrap capacitance when it is low frequency application. FYI the circuit roughly looks as follows:



I am using IRF6894 MOSFET for my application. The bootstrap circuit is different from the conventional one because in the datasheet of AdUM3223, it is recommended to design it likewise.

Kindly recommend how should I approach while designing the bootstrap circuit.

 

[dick_freebird]

I'd start with estimating your worst case charge per cycle (you know t, you know
a (rated) static Icc for the driver so there's that; probably know Qgg for your
FET; have to take a guess at how much of a switching impulse pair's charge you
have to make up). Now figure out what kind of droop you can stand across max
on time (dV) and C=Qsum/dV. Now pad that up some for luck.

Or you could solder a stack of caps up, cut them away one by one until
something starts to stank, and then put a couple back along with a new
driver and FET

 

[abhikuvar]

Thanks a lot. It has raise some more questions. I was going through various websites for helping me up with this particular design and this one came up. https://www.silabs.com/support/Pages/bootstrap-calculator.aspx

So as the frequency goes lower, cap value gets higher according to the website. It increases roughly twice if I am cutting frequency by half.

Also, static ICC means quiescent input supply current, right?

Can you please explain or do you any video or website link that will show details of bootstrap circuit design? (I have went through gate driver design paper by Laszlo Balogh, and I still have these silly doubts here )