#### bigrice911

##### Member level 3

**booth algorithm vhdl code**

Anyone knows about Booth algorithm? It's great help to hardware multiplier, here I got an example which can be your reference.

Also, can somebody help to conversion below VHDL to verilog? It's better to keep the parameterization and use verilog2001 syntax "generate". Thanks!

Code:

```
[b]-------------------------------------
-- Define data width
--
-------------------------------------
package mypackage is
constant NBITS :natural := 7;
constant MBITS :natural := 9;
end mypackage;
---------------------------------------------------------
-- Booth-1 multiplier
--
----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mypackage.all;
entity booth_1 is
port (
X: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
Y: in STD_LOGIC_VECTOR (MBITS-1 downto 0);
P: out STD_LOGIC_VECTOR (NBITS+MBITS-1 downto 0)
);
end booth_1;
architecture simple_arch of booth_1 is
component booth_1_cell
Port ( P : in std_logic_vector(MBITS-1 downto 0);
Y : in std_logic_vector(MBITS-1 downto 0);
x_i : in std_logic_vector(1 downto 0);
S : out std_logic_vector(MBITS downto 0)
);
end component;
type conections is array (0 to NBITS) of STD_LOGIC_VECTOR (MBITS downto 0);
Signal wires: conections;
Signal eX: STD_LOGIC_VECTOR (NBITS downto 0);
begin
eX(NBITS downto 1) <= X; eX(0) <= '0';
wires(0) <= (others => '0');
iterac: for I in 0 to NBITS-1 generate
mult: booth_1_cell port map (P => wires(i)(MBITS downto 1),
Y => Y, x_i => eX(i+1 downto i), S => wires(i+1) );
p(i) <= wires(i+1)(0);
end generate;
p(MBITS+NBITS-1 downto NBITS) <= wires(NBITS)(MBITS downto 1);
end simple_arch; [/b]
```