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# Boost PFC input current has high Second Harmonic and Third Harmonic

#### Longcircuit

##### Newbie
**Subject: High THD on 2nd and 3rd Harmonics of a 5kW Single-Phase UPS**

Hi everyone,

I'm measuring the input current harmonics on a single-phase 5kW UPS with a 120V AC, 60Hz input. I noticed that the Total Harmonic Distortion (THD) is high specifically on the 2nd and 3rd harmonics.the ups has a boost pfc and isolation transformer on input.

**My questions are:**

1. In general, aren't even harmonics (like the 2nd harmonic) usually a sign of a DC offset or asymmetry in the waveform?

2. Can such low-frequency harmonics be effectively filtered using an LC filter, or would other methods be more appropriate?

Hi,

2nd harmonic? Are you sure?

Klaus

your volt loop is too fast - should be << 15Hz

1. In general, aren't even harmonics (like the 2nd harmonic) usually a sign of a DC offset or asymmetry in the waveform?
Second harmonics (and all even harmonics) are, by definition, due to asymmetry of the waveform. DC offset is it's own term (the 0th harmonic, in a sense), so it doesn't directly relate to other harmonics. Though in some circuits, the DC level may greatly impact other harmonics (I don't think that's relevant here though).
2. Can such low-frequency harmonics be effectively filtered using an LC filter, or would other methods be more appropriate?
Basically no. In practice LC filters are meant to reduce higher frequency emissions, in the kHz range an up. In theory one could make a LC filter which significantly attenuates the second harmonic, but the bottom line is "don't bother". It will have major caveats.
your volt loop is too fast - should be << 15Hz
Oh come on, if you're going to spoil the mystery, at least explain it...

No doubt that too fast voltage control loop generates odd harmonics. Controller output gets unwanted 100 Hz component, however by multiplying with 50 Hz reference, even harmonics are canceled. There must be significant asymmetry in power stage to produce 2nd harmonic.

Yes, as Easy Peasy is maybe suggesting, the second harmonic is likely to show up if the volt loop is too fast, and then more current is drawn on one 10ms haversine rather than the next, and so on, and thus you have the second harmonic showing its ugly head.
Also, you get some boost PFCs that are made of two paralleled Boost PFCs...one does one 10ms haversine, and the other does the next 10ms haversine, and so on....obviously with tolerance they may not be symetrical and so you again end up with the second harmonic coming into play.

Yes, you cant relistically filter 2nd and 3rd harmonics.....they are too low frequency and filter would be too big.

Hi, See link below for picture for sketch. I need to do more testing but it seems I only get even harmonics when i parallel the PFCs. If i run 1 PFC by itself no even harmonics. Also the 3rd harmonic high regardless if paralleling or not . In summary id like to find out what i "knob" i need to turn to lower the 2nd and third harmonic. the controller iC is iUC3854BDW. With this additional information does it still seem like an issue with control loop?
 Freq. (Hz) Harmonic Value (A) 60​ Fund. 13.84​ 120​ 2​ 0.69​ 180​ 3​ 1.24​ 240​ 4​ 0.06​ 300​ 5​ 0.56​ 360​ 6​ 0.05​ 420​ 7​ 0.18​ 480​ 8​ 0.05​ 540​ 9​ 0.24​ 600​ 10​ 0.04​ 660​ 11​ 0.25​ 720​ 12​ 0.05​ 780​ 13​ 0.15​ 840​ 14​ 0.04​

2nd harmonic? Are you sure?

Klaus

If you tell us which control IC you're using for the PFC, we can probably tell you specifically what tests to run to determine if excessive voltage loop bandwidth is the cause.

The full diode-bridge acts as a frequency doubler converting 60Hz to 120Hz. That has the effect of increasing 2nd harmonics.

If you tell us which control IC you're using for the PFC, we can probably tell you specifically what tests to run to determine if excessive voltage loop bandwidth is the cause.
Thanks. the control IC is UC3854

again - your volt loop is too fast and your current loop may not be optimised.

The specific PFC topology produces even harmonics if split output is loaded asymmetrically. Depends on inverter topology if this is possible. Assuming symmetrical load, even harmonics are a matter of inappropriate PFC control. How is voltage sense connected?

Yes also, if that split capacitor bank is not comprising equal value capacitors , then there could be an imbalance, causing more 2nd order harmonics.
The schem looks very unusual...i mean, why do isolation with mains transformers?.....way too big at your several kWs. Why not do it with a switch mode stage and a far smaller transformer?

Read the excellent app notes on the UC3854N which cover how to set up the Volt error amp and current loop.

UC3854 also needs Schottky protection of the gate outputs, due to the old fashioned tech inside this albeit excellent part.
Also need schottky protection of the current sense input.
Also, the LT1248 is pretty well the same part as UC3854, so you can check off your cct with a sim of that in the free LTspice.
If you get LT1248 stable (and good PFC) , then UC3854 will also be stable with same values, any scaling accounted for.

again - your volt loop is too fast and your current loop may not be optimised.
AFAIK these can explain odd harmonics but not even...
The specific PFC topology produces even harmonics if split output is loaded asymmetrically. Depends on inverter topology if this is possible.
Assuming symmetrical load, even harmonics are a matter of inappropriate PFC control. How is voltage sense connected?
Oh I didn't even notice that in the simple schematic... the bipolar outputs certainly raise a lot of questions about how Vout/Vin/Iac are sensed...

AFAIK these can explain odd harmonics but not even...
I can imagine that a too fast loop may cause even harmonics. But I don't expect them to be stable. Sometimes it favors the positive half wave, sometimes the negative.
It's fluctuating...

Klaus

The voltage control loop must be compensated for
stability but because the bandwidth of the voltage
loop is so small compared to the switching fre-
quency the requirements for the voltage control
loop are really driven by the need to keep the input
distortion to a minimum rather than by stability. The
loop bandwidth must be low enough to attenuate
the second harmonic of the line frequency on the
output capacitor to keep the modulation of the in-
put current small. The voltage error amplifier must
also have enough phase shift so that what modula-
tion remains will be in phase with the input line to
keep the power factor high.

esp page 3 - 284

2nd harmonic in the AC line current is due to 100/120 Hz wobble in the reference - or similarly synchronised noise getting into the control - usually around the peak of the sine wave, every half cycle as this is where the dv/dt and di/dt is highest in the power stage.

Yes, in order to get zero second harmonic, you would need a totally flat reference to the current error amplifier. The ref to the CEA is obviously provided by the voltage error amplifier...(well its the input voltage half sines multiplied by the error amp factor, so you get the current half sines correctly scaled.).....and realistically its not going to be providing a totally flat reference to the CEA....as that would mean a ridiculously slow bandwidth...and the PFC if not on constant load, would just be bouncing off the upper and lower voltage thresholds continuously.
So some second harmonic is acceptable, but not that much.

Attached please find a LT1248 Boost PFC in LTspice, which you can play with to experiment with the current error amplifier...this ones a led driver so load IS constant.....so i hacked it to give a constant ref from the voltage loop. so to speak, and then you can just concentrate on compensation of the current error amplifier......remember , what you are doing is making the current follow the half sines of voltage.

When you do PFC, you realise that is realistically impossible to get decent PFC if the load is rapidly fluctuating...for a rapidly fluctuating load, some other format than the "standard boost PFC" would be needed to maximise power factor. The standards bodys always test for PF on constant load.....even if the product is one for which the load is never constant.

I suppose a massive output capacitor bank of the PFC could be used in the case of rapidly fluctuating load, though for cost and size reasons, this isnt practical.
--- Updated ---

Attached is a doc giving diffs between LT1248 and UC3854...the '3854 , IF not compensated, has a problem with "line current dead zone"...and this can cause second harmonic to raise its ugly head.
This is where the demand is obviously very low at the mains zero cross.....then, as the demand suddenly builds, the pfc is at first unable to service it...but then overreacts and you get a spike of current just after the zero cross...this can cause 2nd harmonic problem. UC3854 app notes as discussed, tell how to get round this.

#### Attachments

• LT1248 Boost PFC battery charger_1.zip
2.3 KB · Views: 10
• LT1248 vs UC3854.zip
11.7 KB · Views: 11
Last edited:
Yes, in order to get zero second harmonic, you would need a totally flat reference to the current error amplifier. The ref to the CEA is obviously provided by the voltage error amplifier...(well its the input voltage half sines multiplied by the error amp factor, so you get the current half sines correctly scaled.).....and realistically its not going to be providing a totally flat reference to the CEA....as that would mean a ridiculously slow bandwidth...and the PFC if not on constant load, would just be bouncing off the upper and lower voltage thresholds continuously.
So some second harmonic is acceptable, but not that much.

Attached please find a LT1248 Boost PFC in LTspice, which you can play with to experiment with the current error amplifier...this ones a led driver so load IS constant.....so i hacked it to give a constant ref from the voltage loop. so to speak, and then you can just concentrate on compensation of the current error amplifier......remember , what you are doing is making the current follow the half sines of voltage.

When you do PFC, you realise that is realistically impossible to get decent PFC if the load is rapidly fluctuating...for a rapidly fluctuating load, some other format than the "standard boost PFC" would be needed to maximise power factor. The standards bodys always test for PF on constant load.....even if the product is one for which the load is never constant.

I suppose a massive output capacitor bank of the PFC could be used in the case of rapidly fluctuating load, though for cost and size reasons, this isnt practical.
--- Updated ---

Attached is a doc giving diffs between LT1248 and UC3854...the '3854 , IF not compensated, has a problem with "line current dead zone"...and this can cause second harmonic to raise its ugly head.
This is where the demand is obviously very low at the mains zero cross.....then, as the demand suddenly builds, the pfc is at first unable to service it...but then overreacts and you get a spike of current just after the zero cross...this can cause 2nd harmonic problem. UC3854 app notes as discussed, tell how to get round this.
Thankyou for the detailed response I'm going to dig into the control loop and look into simulating circuit with the files you provided