Blocking & Non- Blocking

[kunal1514]

Hi All,

I am having a very interested query for you

initial--------------- case - 1
begin
a <= 1'b1;
a <= 1'b0;
end-----------------



initial--------------- case - 2
begin
a = 1'b0;
a <= 1'b1;
end-----------------

Question what will be the value of "a" in both the cases. Also specify simulator name. Also mention why after giving the answer.

 

[subramanyam]

In the first case the a is '0' and in the second case a = 1 ;

I think , in this case the answer is independent of the simulator . This is bcoz whatever may be the simulator the basic defintion of these blocking and non blocking have to be implemented by them.

1) In first case , both the statements have calculated thier RHS at the start of the time step and are updated at the end of the step . but the last updated is the second statement (as in side always they are sequential) , so is the answer '0'.

2)In the second case , according to the defintion , after the calculation of RHS and the updation of the blocking then only the second statement is executed , so is the answer '1'.

I think , the variations in the results on different simulators occurs when there is a race condition , which is not a case here.

what do u think guys ... plz correct me if i am wrong .

subbu

 

[ankit12345]

for the first case my simulator got hanged......both in linux and windows....................

 

[aji_vlsi]

for the first case my simulator got hanged......both in linux and windows....................

Did it really hang or simply got stuck at time zero due to lack of events? In the sample code you showed, there is no time being progressed, hence it might look like a hang. Which simulator do you use? If you need more help, show us the complete code.

Regards
Ajeetha, CVC
www.noveldv.com

 

[shahal]

initial--------------- case - 1
begin
a <= 1'b1;
a <= 1'b0;
end-----------------

initial--------------- case - 2
begin
a = 1'b0;
a <= 1'b1;
end-----------------

There is a difference in the codes between case 1 and case 2. Look Carefully, I am not sure if that difference is causing it to hang.

 

[mallikmarasu]

see in the first case inside begin-end non blocking statements are there.

so for the non blocking statements ,simulator first caluclate the right handed side
expression for all the non blocking statements at zero simulation time .after that
i.e in the second stage caluclated expressions are assigned to left hand sided .

in this case -1, for a<=1 ,
a<=0
simulator assign one to temp_1 register
and zero to temp_2 in the first phase at zero simulation time.
second phase ,
simulator will try to assign these temp_1 ,temp_2 to a at the same time.for a single variable at same time how u can assign two values.
so that simulator should hanged.

suppose in the above if u r assigneing to differnt variables i.e suppose
a<=1,b<=0 then no problem at all.
or other wise a<=1,
#1 a <=0;
here also no problem.
or other wise a<=1,
a<=1;
same value to the one variables here also no problem
so,for a single varaible assigning two different values at particular time is not allowed

if i am wrong please correct me

Added after 4 minutes:

for case-2 ,a=1,
a<=0;

here no problem first a =1 executed because this is blocking.
after the first stament over next statement executed .
so finally a value is zero.

if i am wrong please correct me.

 

[matthew_wang]

Could some give out the result by run simulation in some simulation?

 

[verilog_always]

For the first case I had run differrent types...
1.a<=1'b0;a<=1'b1;
2.a<=1'b1;a<=1'b0;

in the first case I got the value of a=1 and in next case I got a=0; So, i think when same output is driven it will take last value,since it is executed at last(or simulator dependent)... Am I right ?

 

[ankit12345]

Try in diff simul;ators and check................then we can come to some conclusion.....

 

[rangans]

Both will give errors in PKS shell, cadence's simulator. The first is worng as you are trying to use two non-blocking assigments to assign different values to the same variablw in the same time step which is not possible. The second gives asn error because you are trying to combine a non-blocking and blocking assign in the same always block which cannot be synthesized in any proper way where the results are predictable. hence the error.

 

[kunal1514]

Hi All,

for last persons reply these are "initial" blocks not always and they are very much possible.

 

[zhangpengyu]

for case-1 a=0;
for case-2 a=1;
according to the event schedule of IEEE standard;

 

[subramanyam]

Hii ,

Can any one tell about this IEEE standard of event scheduling in verilog ???
How the events are scheduled in verilog?? Please attach some information regarding this.

subbu.

 

[nmurthy]

This is wrt Modelsim,

correct me if i am wrong

in first case

a will be 1 ---- bcoz in race of NBA ,last NBA wins

and in next case

a will be 0 ---- bcoz in race of NBA and BA ,last BA wins

hope it helped you

 

[vcnvcc]

Hi nmurthy

This is also wrt Modelsim

BUT for this quest i am getting this

Q - initial
begin
b <= 1'b1;
b = 1'b0;
end ANS is 1.

Q - initial
begin
b = 1'b1;
b <= 1'b0;
end ANS is still 1.


so please explain " in race of NBA and BA ,last BA wins"
(NBA--Non blocking assignment...)