blocking and non-blocking statements in verilog?

[want2LearnVlsi]

blocking and non blocking in verilog

Hi,

Can anybody explain the concepts of Blocking and Non-blocking statements in Verilog? Or any good book/paper explaining these clearly..?
I just started learning Verilog and I am getting confused when to use these statements.
Thanks in advance.

KSSR

 

[hemanth]

blocking vs non blocking verilog

check out this one, hope this one is useful

https://www.asic-world.com/tidbits/blocking.html

 

[FvM]

verilog blocking statements examples

A classical paper discussing the topic in detail:

 

[kvingle]

verilog non blocking

The paper posted above is really useful....
again you can check "verilog FAQ" book in the forum it also spelled nice differences ...

 

[want2LearnVlsi]

verilog blocking vs non-blocking

Hi All,

Thanks for the replies.
I will go thru the mentioned documents.

KSSR

 

[gck]

To get more insight on blocking and non blocking visit following link

**broken link removed**

 

[karikalan_t79]

best book is verilog by j bhasker its has clear example and snug paper

 

[bvprulz]

A very basic example:
Blocking statement: Sequential
A = 0 and B=1 then
A=B //A = 1
B=A //B = 1

Nonblocking statement:
A=0 and B=1 then
A=B //A=1
B=A //B=0

Hope this helps..

 

[dpaul81]

A quick explanation from the useage point of view...guess it would be useful!

1> Use of non-blocking statements:
Use it only within SEQUENTIAL 'always' blocks (eg - if the sensitivity list contains a clock signal). A blocking statement here can cause Verilog race conditions.

2> Use of blocking st:
Use blocking assignments for combinational 'always' blocks.