In addition to reset signals, other control logic can prevent memory logic from being
inferred as a memory block. For example, you cannot use a clock enable on the read
address registers in Stratix® devices because doing so affects the output latch of the
RAM, and therefore the synthesized result in the device RAM architecture would not
match the HDL description. You can use the address stall feature as a read address
clock enable in Stratix II, Cyclone® II, Arria® GX, and other newer devices to avoid
this limitation. Check the documentation for your device architecture to ensure that
your code matches the hardware available in the device.