After another round of thorough investigation, I finally nail down the root cause of this persitent error: Read Address bus setup/hold timing violation. One logic input driving this address bus is sourced from tri-state data bus external to the FPGA. Due to logic optimation, there is possible unknown logic state 'X' driving the address line, hence causing timing problem. And in the VHD, I did assign the address bus with 'X' state when I don't care about the read data.
Regards
ZFYoung