I am trying to implement Cache emulator on Virtex-II pro(VHDL).
i wish to use the block RAM available to form cache of 1KB, i dont have any idea about how to use Block RAM and i couldnt follow any online material for the same.
can anybody explain this or suggest some reading material, website or something.
i have generated the BRAM 512x32 using CoreGen and its working fine.......but i didnt initialize it.....
i wish to initialize the RAM with some data..........from internet i learned that either i have to write a .COE file or use an Initialization template......i m confused abt to use these....
can you tell me the exact way to do this.
i think it is same as the .coe syntax given on Xilinx website..........can i copy paste this in a text file with .coe extention and attach it with the BRAM ?