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BLOCK placement in innovus

S

Saati

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Hi all,
I use PVDD2ANA and PVSS2ANA for the Analog macro as power and ground IO cell.
Based on TSMC databook for IO cell, this IO cell needed PCLAM2ANA for ESD protection. The PCLAM2ANA cell is defined as "CLASS BLOCK" in LEF file. Now, I want to place the PCLAM2ANA in my design near the PVDD2ANA and PVSS2ANA. How does this? And what command is used to place macros that are not in the netlist?

Thanks & Regards
Saati
 
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ThisIsNotSam said:
are you sure this is a macro and not a pad?
Click to expand...
It's in pad library but the site of that is not pad.
for example the bellow shows the pad and corner site and PCLAMP1ANA and PDUW0204CDG (as digital IO).
Code: 
SITE pad
    SYMMETRY x y r90 ;
    CLASS pad ;
    SIZE 0.005 BY 130.000 ;
END pad 

SITE corner
    SYMMETRY x y r90 ;
    CLASS pad ;
    SIZE 130.000 BY 130.000 ;
END corner

MACRO PCLAMP1ANA
    CLASS BLOCK ;
    FOREIGN PCLAMP1ANA 0.000 0.000  ;
    ORIGIN 0.000 0.000 ;
    SIZE 81.790 BY 65.000 ;
    SYMMETRY X Y R90 ;
    PIN VSSESD
        DIRECTION INOUT ;
        PORT
        LAYER METAL3 ;
        RECT  6.510 0.000 41.510 65.000 ;
        END
    END VSSESD
    PIN VDDESD
        DIRECTION INOUT ;
        PORT
        LAYER METAL3 ;
        RECT  42.640 0.000 75.930 65.000 ;
        END
    END VDDESD
    OBS
        LAYER METAL1 ;
        RECT  0.000 0.000 81.790 65.000 ;
        LAYER METAL2 ;
        RECT  0.000 0.000 81.790 65.000 ;
        LAYER VIA23 ;
        RECT  42.640 0.000 75.930 65.000 ;
        RECT  6.510 0.000 41.510 65.000 ;
        LAYER METAL3 ;
        RECT  76.530 0.000 81.790 65.000 ;
        RECT  0.000 0.000 5.910 65.000 ;
    END
END PCLAMP1ANA

MACRO PDUW0204CDG
    CLASS PAD ;
    FOREIGN PDUW0204CDG 0.000 0.000  ;
    ORIGIN 0.000 0.000 ;
    SIZE 60.000 BY 85.000 ;
    SYMMETRY X Y R90 ;
    SITE pad ;
    PIN PE
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  31.195 84.000 34.535 85.000 ;
        LAYER METAL3 ;
        RECT  31.195 84.000 34.535 85.000 ;
        LAYER METAL2 ;
        RECT  31.195 84.000 34.535 85.000 ;
        LAYER METAL1 ;
        RECT  31.195 84.000 34.535 85.000 ;
        END
    END PE
    PIN PAD
        DIRECTION INOUT ;
        PORT
        LAYER METAL4 ;
        RECT  2.500 0.000 57.500 3.160 ;
        LAYER METAL3 ;
        RECT  2.500 0.000 57.500 3.160 ;
        LAYER METAL2 ;
        RECT  2.500 0.000 57.500 2.020 ;
        LAYER METAL1 ;
        RECT  2.500 0.000 57.500 1.095 ;
        END
    END PAD
    PIN OEN
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  17.255 84.000 20.595 85.000 ;
        LAYER METAL3 ;
        RECT  17.255 84.000 20.595 85.000 ;
        LAYER METAL2 ;
        RECT  17.255 84.000 20.595 85.000 ;
        LAYER METAL1 ;
        RECT  17.255 84.000 20.595 85.000 ;
        END
    END OEN
    PIN IE
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  36.145 84.000 39.485 85.000 ;
        LAYER METAL3 ;
        RECT  36.145 84.000 39.485 85.000 ;
        LAYER METAL2 ;
        RECT  36.145 84.000 39.485 85.000 ;
        LAYER METAL1 ;
        RECT  36.145 84.000 39.485 85.000 ;
        END
    END IE
    PIN I
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL3 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL2 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL1 ;
        RECT  3.180 84.000 6.520 85.000 ;
        END
    END I
    PIN DS
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  27.010 84.000 30.350 85.000 ;
        LAYER METAL3 ;
        RECT  27.010 84.000 30.350 85.000 ;
        LAYER METAL2 ;
        RECT  27.010 84.000 30.350 85.000 ;
        LAYER METAL1 ;
        RECT  27.010 84.000 30.350 85.000 ;
        END
    END DS
    PIN C
        DIRECTION OUTPUT ;
        PORT
        LAYER METAL4 ;
        RECT  43.710 84.000 47.050 85.000 ;
        LAYER METAL3 ;
        RECT  43.710 84.000 47.050 85.000 ;
        LAYER METAL2 ;
        RECT  43.710 84.000 47.050 85.000 ;
        LAYER METAL1 ;
        RECT  43.710 84.000 47.050 85.000 ;
        END
    END C
    OBS
        LAYER METAL1 ;
        RECT  57.730 0.000 60.000 85.000 ;
        RECT  47.280 1.325 57.730 85.000 ;
        RECT  43.480 1.325 47.280 83.770 ;
        RECT  39.715 1.325 43.480 85.000 ;
        RECT  35.915 1.325 39.715 83.770 ;
        RECT  34.765 1.325 35.915 85.000 ;
        RECT  30.965 1.325 34.765 83.770 ;
        RECT  30.580 1.325 30.965 85.000 ;
        RECT  26.780 1.325 30.580 83.770 ;
        RECT  20.825 1.325 26.780 85.000 ;
        RECT  17.025 1.325 20.825 83.770 ;
        RECT  6.750 1.325 17.025 85.000 ;
        RECT  2.950 1.325 6.750 83.770 ;
        RECT  2.270 1.325 2.950 85.000 ;
        RECT  0.000 0.000 2.270 85.000 ;
        LAYER VIA12 ;
        RECT  2.500 0.000 57.500 2.020 ;
        RECT  43.710 84.000 47.050 85.000 ;
        RECT  36.145 84.000 39.485 85.000 ;
        RECT  31.195 84.000 34.535 85.000 ;
        RECT  27.010 84.000 30.350 85.000 ;
        RECT  17.255 84.000 20.595 85.000 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL2 ;
        RECT  57.780 0.000 60.000 85.000 ;
        RECT  47.330 2.300 57.780 85.000 ;
        RECT  43.430 2.300 47.330 83.720 ;
        RECT  39.765 2.300 43.430 85.000 ;
        RECT  35.865 2.300 39.765 83.720 ;
        RECT  34.815 2.300 35.865 85.000 ;
        RECT  30.915 2.300 34.815 83.720 ;
        RECT  30.630 2.300 30.915 85.000 ;
        RECT  26.730 2.300 30.630 83.720 ;
        RECT  20.875 2.300 26.730 85.000 ;
        RECT  16.975 2.300 20.875 83.720 ;
        RECT  6.800 2.300 16.975 85.000 ;
        RECT  2.900 2.300 6.800 83.720 ;
        RECT  2.220 2.300 2.900 85.000 ;
        RECT  0.000 0.000 2.220 85.000 ;
        LAYER VIA23 ;
        RECT  2.500 0.000 57.500 3.160 ;
        RECT  43.710 84.000 47.050 85.000 ;
        RECT  36.145 84.000 39.485 85.000 ;
        RECT  31.195 84.000 34.535 85.000 ;
        RECT  27.010 84.000 30.350 85.000 ;
        RECT  17.255 84.000 20.595 85.000 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL3 ;
        RECT  57.780 0.000 60.000 85.000 ;
        RECT  47.330 3.440 57.780 85.000 ;
        RECT  43.430 3.440 47.330 83.720 ;
        RECT  39.765 3.440 43.430 85.000 ;
        RECT  35.865 3.440 39.765 83.720 ;
        RECT  34.815 3.440 35.865 85.000 ;
        RECT  30.915 3.440 34.815 83.720 ;
        RECT  30.630 3.440 30.915 85.000 ;
        RECT  26.730 3.440 30.630 83.720 ;
        RECT  20.875 3.440 26.730 85.000 ;
        RECT  16.975 3.440 20.875 83.720 ;
        RECT  6.800 3.440 16.975 85.000 ;
        RECT  2.900 3.440 6.800 83.720 ;
        RECT  2.220 3.440 2.900 85.000 ;
        RECT  0.000 0.000 2.220 85.000 ;
        LAYER VIA34 ;
        RECT  2.500 0.000 57.500 3.160 ;
        RECT  43.710 84.000 47.050 85.000 ;
        RECT  36.145 84.000 39.485 85.000 ;
        RECT  31.195 84.000 34.535 85.000 ;
        RECT  27.010 84.000 30.350 85.000 ;
        RECT  17.255 84.000 20.595 85.000 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL4 ;
        RECT  57.780 0.000 60.000 85.000 ;
        RECT  47.330 3.440 57.780 85.000 ;
        RECT  43.430 3.440 47.330 83.720 ;
        RECT  39.765 3.440 43.430 85.000 ;
        RECT  35.865 3.440 39.765 83.720 ;
        RECT  34.815 3.440 35.865 85.000 ;
        RECT  30.915 3.440 34.815 83.720 ;
        RECT  30.630 3.440 30.915 85.000 ;
        RECT  26.730 3.440 30.630 83.720 ;
        RECT  20.875 3.440 26.730 85.000 ;
        RECT  16.975 3.440 20.875 83.720 ;
        RECT  6.800 3.440 16.975 85.000 ;
        RECT  2.900 3.440 6.800 83.720 ;
        RECT  2.220 3.440 2.900 85.000 ;
        RECT  0.000 0.000 2.220 85.000 ;
    END
END PDUW0204CDG
Now how to place PCLAM1ANA (or PCLAM2ANA) that there is not in verilog netlist ?

Thanks & Regards
Saati
 
Last edited by a moderator:
Upvote 0 Downvote
something like (not sure about innovus notation):
create_cell u1 PCLAMP1ANA
set_cell_location u1 x y
connect_net VDD u1/vdd
connect_net VSS u1/vss
 
Upvote 0 Downvote
oratie said:
something like (not sure about innovus notation):
create_cell u1 PCLAMP1ANA
set_cell_location u1 x y
connect_net VDD u1/vdd
connect_net VSS u1/vss
Click to expand...
Thanks for reply.
The "create_cell" or "create_inst" does not exist in innovus.
Do you know the right command?

Thanks & Regards
Saati
 
Upvote 0 Downvote
I have seen ESD cells that are not pads, they are meant to be used with flip-chip where you can have VDD/VSS being delivered without a pad ring. So it becomes the designer's responsibility to manage ESD. The cell you pointed out might be one of those.

If it indeed is a macro, you can place it by hand using innovus GUI. You can set its x and y coordinates by commands. You can let the tool do the placement automatically. You can also do relative placement with respect to other cells/pads. There are a million ways to get a floorplan done.
 
Upvote 0 Downvote
ThisIsNotSam said:
I have seen ESD cells that are not pads, they are meant to be used with flip-chip where you can have VDD/VSS being delivered without a pad ring. So it becomes the designer's responsibility to manage ESD. The cell you pointed out might be one of those.

If it indeed is a macro, you can place it by hand using innovus GUI. You can set its x and y coordinates by commands. You can let the tool do the placement automatically. You can also do relative placement with respect to other cells/pads. There are a million ways to get a floorplan done.Thanks
Click to expand...
Thanks for your answer.
How can place MACROs in GUI in innovus?
Which toolbar used for this.

Thanks & Regards
Saati
 
Upvote 0 Downvote
Saati said:
It's in pad library but the site of that is not pad.
for example the bellow shows the pad and corner site and PCLAMP1ANA and PDUW0204CDG (as digital IO).
Code: 
SITE pad
    SYMMETRY x y r90 ;
    CLASS pad ;
    SIZE 0.005 BY 130.000 ;
END pad

SITE corner
    SYMMETRY x y r90 ;
    CLASS pad ;
    SIZE 130.000 BY 130.000 ;
END corner

MACRO PCLAMP1ANA
    CLASS BLOCK ;
    FOREIGN PCLAMP1ANA 0.000 0.000  ;
    ORIGIN 0.000 0.000 ;
    SIZE 81.790 BY 65.000 ;
    SYMMETRY X Y R90 ;
    PIN VSSESD
        DIRECTION INOUT ;
        PORT
        LAYER METAL3 ;
        RECT  6.510 0.000 41.510 65.000 ;
        END
    END VSSESD
    PIN VDDESD
        DIRECTION INOUT ;
        PORT
        LAYER METAL3 ;
        RECT  42.640 0.000 75.930 65.000 ;
        END
    END VDDESD
    OBS
        LAYER METAL1 ;
        RECT  0.000 0.000 81.790 65.000 ;
        LAYER METAL2 ;
        RECT  0.000 0.000 81.790 65.000 ;
        LAYER VIA23 ;
        RECT  42.640 0.000 75.930 65.000 ;
        RECT  6.510 0.000 41.510 65.000 ;
        LAYER METAL3 ;
        RECT  76.530 0.000 81.790 65.000 ;
        RECT  0.000 0.000 5.910 65.000 ;
    END
END PCLAMP1ANA

MACRO PDUW0204CDG
    CLASS PAD ;
    FOREIGN PDUW0204CDG 0.000 0.000  ;
    ORIGIN 0.000 0.000 ;
    SIZE 60.000 BY 85.000 ;
    SYMMETRY X Y R90 ;
    SITE pad ;
    PIN PE
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  31.195 84.000 34.535 85.000 ;
        LAYER METAL3 ;
        RECT  31.195 84.000 34.535 85.000 ;
        LAYER METAL2 ;
        RECT  31.195 84.000 34.535 85.000 ;
        LAYER METAL1 ;
        RECT  31.195 84.000 34.535 85.000 ;
        END
    END PE
    PIN PAD
        DIRECTION INOUT ;
        PORT
        LAYER METAL4 ;
        RECT  2.500 0.000 57.500 3.160 ;
        LAYER METAL3 ;
        RECT  2.500 0.000 57.500 3.160 ;
        LAYER METAL2 ;
        RECT  2.500 0.000 57.500 2.020 ;
        LAYER METAL1 ;
        RECT  2.500 0.000 57.500 1.095 ;
        END
    END PAD
    PIN OEN
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  17.255 84.000 20.595 85.000 ;
        LAYER METAL3 ;
        RECT  17.255 84.000 20.595 85.000 ;
        LAYER METAL2 ;
        RECT  17.255 84.000 20.595 85.000 ;
        LAYER METAL1 ;
        RECT  17.255 84.000 20.595 85.000 ;
        END
    END OEN
    PIN IE
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  36.145 84.000 39.485 85.000 ;
        LAYER METAL3 ;
        RECT  36.145 84.000 39.485 85.000 ;
        LAYER METAL2 ;
        RECT  36.145 84.000 39.485 85.000 ;
        LAYER METAL1 ;
        RECT  36.145 84.000 39.485 85.000 ;
        END
    END IE
    PIN I
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL3 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL2 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL1 ;
        RECT  3.180 84.000 6.520 85.000 ;
        END
    END I
    PIN DS
        DIRECTION INPUT ;
        PORT
        LAYER METAL4 ;
        RECT  27.010 84.000 30.350 85.000 ;
        LAYER METAL3 ;
        RECT  27.010 84.000 30.350 85.000 ;
        LAYER METAL2 ;
        RECT  27.010 84.000 30.350 85.000 ;
        LAYER METAL1 ;
        RECT  27.010 84.000 30.350 85.000 ;
        END
    END DS
    PIN C
        DIRECTION OUTPUT ;
        PORT
        LAYER METAL4 ;
        RECT  43.710 84.000 47.050 85.000 ;
        LAYER METAL3 ;
        RECT  43.710 84.000 47.050 85.000 ;
        LAYER METAL2 ;
        RECT  43.710 84.000 47.050 85.000 ;
        LAYER METAL1 ;
        RECT  43.710 84.000 47.050 85.000 ;
        END
    END C
    OBS
        LAYER METAL1 ;
        RECT  57.730 0.000 60.000 85.000 ;
        RECT  47.280 1.325 57.730 85.000 ;
        RECT  43.480 1.325 47.280 83.770 ;
        RECT  39.715 1.325 43.480 85.000 ;
        RECT  35.915 1.325 39.715 83.770 ;
        RECT  34.765 1.325 35.915 85.000 ;
        RECT  30.965 1.325 34.765 83.770 ;
        RECT  30.580 1.325 30.965 85.000 ;
        RECT  26.780 1.325 30.580 83.770 ;
        RECT  20.825 1.325 26.780 85.000 ;
        RECT  17.025 1.325 20.825 83.770 ;
        RECT  6.750 1.325 17.025 85.000 ;
        RECT  2.950 1.325 6.750 83.770 ;
        RECT  2.270 1.325 2.950 85.000 ;
        RECT  0.000 0.000 2.270 85.000 ;
        LAYER VIA12 ;
        RECT  2.500 0.000 57.500 2.020 ;
        RECT  43.710 84.000 47.050 85.000 ;
        RECT  36.145 84.000 39.485 85.000 ;
        RECT  31.195 84.000 34.535 85.000 ;
        RECT  27.010 84.000 30.350 85.000 ;
        RECT  17.255 84.000 20.595 85.000 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL2 ;
        RECT  57.780 0.000 60.000 85.000 ;
        RECT  47.330 2.300 57.780 85.000 ;
        RECT  43.430 2.300 47.330 83.720 ;
        RECT  39.765 2.300 43.430 85.000 ;
        RECT  35.865 2.300 39.765 83.720 ;
        RECT  34.815 2.300 35.865 85.000 ;
        RECT  30.915 2.300 34.815 83.720 ;
        RECT  30.630 2.300 30.915 85.000 ;
        RECT  26.730 2.300 30.630 83.720 ;
        RECT  20.875 2.300 26.730 85.000 ;
        RECT  16.975 2.300 20.875 83.720 ;
        RECT  6.800 2.300 16.975 85.000 ;
        RECT  2.900 2.300 6.800 83.720 ;
        RECT  2.220 2.300 2.900 85.000 ;
        RECT  0.000 0.000 2.220 85.000 ;
        LAYER VIA23 ;
        RECT  2.500 0.000 57.500 3.160 ;
        RECT  43.710 84.000 47.050 85.000 ;
        RECT  36.145 84.000 39.485 85.000 ;
        RECT  31.195 84.000 34.535 85.000 ;
        RECT  27.010 84.000 30.350 85.000 ;
        RECT  17.255 84.000 20.595 85.000 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL3 ;
        RECT  57.780 0.000 60.000 85.000 ;
        RECT  47.330 3.440 57.780 85.000 ;
        RECT  43.430 3.440 47.330 83.720 ;
        RECT  39.765 3.440 43.430 85.000 ;
        RECT  35.865 3.440 39.765 83.720 ;
        RECT  34.815 3.440 35.865 85.000 ;
        RECT  30.915 3.440 34.815 83.720 ;
        RECT  30.630 3.440 30.915 85.000 ;
        RECT  26.730 3.440 30.630 83.720 ;
        RECT  20.875 3.440 26.730 85.000 ;
        RECT  16.975 3.440 20.875 83.720 ;
        RECT  6.800 3.440 16.975 85.000 ;
        RECT  2.900 3.440 6.800 83.720 ;
        RECT  2.220 3.440 2.900 85.000 ;
        RECT  0.000 0.000 2.220 85.000 ;
        LAYER VIA34 ;
        RECT  2.500 0.000 57.500 3.160 ;
        RECT  43.710 84.000 47.050 85.000 ;
        RECT  36.145 84.000 39.485 85.000 ;
        RECT  31.195 84.000 34.535 85.000 ;
        RECT  27.010 84.000 30.350 85.000 ;
        RECT  17.255 84.000 20.595 85.000 ;
        RECT  3.180 84.000 6.520 85.000 ;
        LAYER METAL4 ;
        RECT  57.780 0.000 60.000 85.000 ;
        RECT  47.330 3.440 57.780 85.000 ;
        RECT  43.430 3.440 47.330 83.720 ;
        RECT  39.765 3.440 43.430 85.000 ;
        RECT  35.865 3.440 39.765 83.720 ;
        RECT  34.815 3.440 35.865 85.000 ;
        RECT  30.915 3.440 34.815 83.720 ;
        RECT  30.630 3.440 30.915 85.000 ;
        RECT  26.730 3.440 30.630 83.720 ;
        RECT  20.875 3.440 26.730 85.000 ;
        RECT  16.975 3.440 20.875 83.720 ;
        RECT  6.800 3.440 16.975 85.000 ;
        RECT  2.900 3.440 6.800 83.720 ;
        RECT  2.220 3.440 2.900 85.000 ;
        RECT  0.000 0.000 2.220 85.000 ;
    END
END PDUW0204CDG
Now how to place PCLAM1ANA (or PCLAM2ANA) that there is not in verilog netlist ?

Thanks & Regards
Saati
Click to expand...
First of all, you should insert them to your design by command addInst (in Innovus tool). Then, place them to your design.
 
Upvote 0 Downvote
if the macro is not on the verilog netlist, you will get LVS issues later on. just instantiate the damn thing by hand, it is not complicated.
 
Upvote 0 Downvote

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