vcsel_driver
Junior Member level 1
Hi,
I have design synthesized at synplifypro. The edf file and port list file are then moved to the ISE as a black box to synthesized with other HDL design. My problem is the design of black box is optimized away by ISE and at the PnR only other IP is routed. When I have other IP commented and IO of the black box connected as the IO pad, I got only 25 track routed. It seems to me the ISE somehow interpret that the design of black box is useless and remove the whole design. How can I makesure the ISE will implement my design in black box?
thanks.
KK
I have design synthesized at synplifypro. The edf file and port list file are then moved to the ISE as a black box to synthesized with other HDL design. My problem is the design of black box is optimized away by ISE and at the PnR only other IP is routed. When I have other IP commented and IO of the black box connected as the IO pad, I got only 25 track routed. It seems to me the ISE somehow interpret that the design of black box is useless and remove the whole design. How can I makesure the ISE will implement my design in black box?
thanks.
KK