Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

BJT amplifier design help needed

Not open for further replies.


Member level 4
Jul 25, 2008
Reaction score
Trophy points
Activity points
BJT amplifier design


I'm trying to design an amplifier which converts 5mV to 4V.
I'm using two 2N2222s and pspice.
The design is consisted of 2 common emmiter stages and the load is not currently important (I have put a 1k resistor as the load).
Each stage has a gain of almost 40.
The problem is that the second stage completely distorts the signal.

Can any one help me,please ?
Thank you very much in advance.

The schematics image and spice files are uploaded.

if you have a total gain of 1600, (40*40) you have 8V output after the second stage!!
You only need a total gain of 800, i.. a gain of 30 in each stage.

The emitter is at about 1V and the collector is at about 7V so the collector can swing only 2V before the transistor is cutoff. The 1k load reduces the max output swing to 1V peak.
So you cannot have an output of 4V.

Thank you ,
I have changed the circuit like this : the collector voltage is about 4.3V and the total gain is about 800 (I tested the circuit with 1uV input) but I still can't see a pure sine wave for a 5mV input.

What can I do ?
Is it totally possible to make such amplifier ?

Thank you

If I read your circuit correctly, your 1st stage should have a gain of about 80. If your 2nd stage gain is 40, which I think it is, then the 1st stage has a load that is almost 2x higher than the load of the 2nd stage for the same gm, hence gain of 80. In this case with 5mv input, the output should go beyond the supply.

Sorry, I didn't see you posted another circuit. What I said was for the first one.

Now your first transistor is nearly cutoff and the second transistor is saturated because they are biased wrong.

The input resistance of the second stage is 4.97KΩ ,applying the to the firs stage ,the total gain of the first stage is about 24.5 .
The total gain of the second stage including the 1KΩ load is about 29.2 .

so the total gain is about 715 the converts 5mV to 3.57 V .
I think the total gain of the circuit is in fact less that 715 because I excluded the effect of first stage's output resistance.

I don't know why the circuit is not working yet :(

Added after 12 minutes:

Looks like I have to make some fundamental changes.

Can you please introduce me some books about this matter.

I have already read books like Sedra Smith and Razavi .They do not deal with design techniques directly.

Thank you.

I tend to disagree with what you say. Based on your second schematic, you have 880mV at the base of the 2nd stage transistor and if we assume Vbe=0.6v, the emitter voltage is 280mV, which with the emitter resistor of 100, forces Ic=2.8mA. If we assume the thermal voltage Vt=26mV, then your gm2=Ic/Vt=108mS. The input resistance of the stage is rpi=β/gm2=1k if β=100 and 3k if β=300. But let's be pessimistic and assume β=100 and rpi2=1k. The load to the 1st stage is then 500||1k=330. For the first stage Ic=2.2mA, which means gm1=85mS and rpi1=1.1k. So the gain of the 1st stage is 85mS*330=28, the gain of the second stage is 108mS*820=88. You have some resistor divider at the input with ratio of 0.64, so the total gain is 0.64*28*88=1578. A 5mV input will try to produce 7.9v at the output. But there is also another problem - one that ruins your circuit. The biasing of the 2nd stage tries to force Ic=2.8mA. Your collector resistance there is 4.5k. Then the collector DC voltage should be 9-2.8mA*4.5k=-3.6v and your second bjt is gone, very saturated.

I already said that the transistors are biased wrong.
The first transistor is nearly cutoff and the second transistor is saturated. Then they do not amplify anything.

Why do you think the 1st transistor is cut-off?

The first transistor is nearly cutoff because its collector voltage is almost at the supply voltage instead of being half-way between the emitter voltage and the supply voltage.

The second transistor is saturated because its collector and emitter voltages are the same.

I don't think this qualifies as a "cut-off". Collector is indeed at 8v, so you have a whole 1v distance to the supply voltage. The gain of the 1st stage is roughly 30 and if we disregard the input voltage division, then the swing at the output of the 1st stage is 150mV peak. It can't reach the supply at all.

It should be biased at 5V, not 8V. It is wrong and the slightest change in a resistor value will cause it to fail.

Why not bias it properly?

Yes, I agree that a proper way of biasing would be one producing something like Vcc/2, more or less. But given the current design and its issues, 1st stage is hardly a concern in this respect. It works with rather small signals. If we want to really clip the 1st stage output, for the same bias current we'll need to reduce the collector resistance by 400 ohm which is a lot to be considered as a statistical variation around the chosen value of 500 ohm and could hardly be called "the slightest change".

I calculated voltages that are with typical resistor and hFE values and the transistor was close to cutoff.
Now try each of the 4 resistors at plus or minus 5% and with low hFE to see if the transistor clips the signal.

OK, I didn't simulate, just did a rough calculation. If I change the resistors by about +-10%, which is:
R1=55k; R2=10k; R3=500; R4=450 and assume β=50, I get Ic=1.18mA and a collector voltage of 8.5v. And I think this is still ok for an output amplitude of 150mv peak. However, note that since Ic dropped in value, gm1 is also smaller (about 2x), R4 is smaller, so the gain of 1st stage is smaller by about 2x. And actually, we don't have 150mV but about 70-80mv, so no problem in clipping the signal.

But we have already agreed that under normal circumstances this would be the right way to go. What I was trying to say so far was that yes, the 1st stage can be improved, but it is not the show-stopper right now.

The show stopper is that the output transistor is wrongly biased so it is saturated.

It is simple to properly bias transistors. Why wasn't it done correctly? Random?

Here I completely agree. But that's why the guy needed help.

Not open for further replies.

Part and Inventory Search

Welcome to