bitstream by Xilinx system generator

[alimassster]

xilinx bitstream

Does SysGen produce a bitstream file to be downloaded in any FPGA
If yes , how is it possible without place & route and so on?
thx in adv

 

[echo47]

xilinx hdl to bitstream

No, Xilinx System Generator outputs HDL and EDIF modules. If you want a bitstream, you also need ISE to do the place & route.

If your project is straightforward, System Generator can run the ISE tools for you, without using Project Navigator.

 

[alimassster]

free version+xilinx system generator

I asked that because of this part of UserGuide attached

 

[echo47]

generate bitstream in ise

The System Generator documentation and advertising are confusing. See User Guide section "Software Prerequisites". Also see this page:
**broken link removed**

System Generator may be partially usable without full ISE, but most users would never want to do that because only ISE provides place & route. This old Answer Record may be helpful to somebody:
**broken link removed**

 

[alimassster]

xilinx system generator memory

echo47 I'm confused with a concept . I wonder if you can halp me .
in virtex-4 sx55 DSP48 block , in order to implement a 64-tap FIR using 64 MUL block in parallel , are inputs stored in memory and then fed into multipliers simultaneously OR with a delay one by one as a stream by using BCIN-BCOUT?
and if so(one by one inputing) then how does using 64 multipliers make a better performance? and how do we have an output in each clk cycle?
is it because of using pipeline?

I read dsp48 userguide to get the advantages of parallelism but got more confused .

maybe you can gimme a hand buddy

 

[echo47]

system generator to ise

If you use only one multiplier and one adder, each 64-tap FIR calculation will take 64 clock cycles.
If you use 64 multipliers and 64 adders, each 64-tap FIR calculation will take only one clock cycle.
Both methods have several clock cycles of latency, but that probably won't affect your overall system throughput.

Your block diagram shows a good way to build an 8-tap parallel FIR in a Virtex-4. You can easily expand it to 64 taps. I'm not sure which Xilinx paper you are reading, so to understand how this structure works, try reading section "Systolic FIR Filter" in this free Xilinx book:
"DSP: Designing for Optimal Results"
https://www.xilinx.com/publications/books/dsp/index.htm

"X" is your input data, one word per clock. The "h" inputs are your filter coefficients. "Y" is the filtered output data, one word per clock. If you have difficulty understanding the (somewhat confusing) pipeline in this design, try starting at the beginning of Chapter 5 "Parallel FIR Filters", and observe how they evolve the basic FIR design into the systolic design.

 

[alimassster]

what is bitstream xilinx

Thank you honey
I'm going to present my seminar on thursday let's see what happens
I'm going to master FPGA implementation techniques so it'll be very nice to be in touch with you . this is my Email address : alimassster@gmail.com
Wish you the best
take good care and keep in touch