hi,
sorry for the late reply, forgot to check this topic..
You could, of course, build a state machine from ttl/cmos msi parts to do this job, but I sense that would violate the spirit of your specification.
Heh, 'violate the spirit of your specification', I like that...its true as well. I have used a CPLD, and considering I don't really have any background in desinging comms chips per se, I just used common sense. . .
An 8-bit shift-register, with a buffer that automatically loads the SR with the next byte, once the first has been sent, so I can 'stream' bits continuously for ever, without any gaps in timing (as long as I provide bytes). Of course, the 'framing' you mentioned would simply be a byte of preamble, and a 'sync byte'. I was going to use 'manchester encoding' on-the-fly (encoding one bit at a time) but in a microcontorller, its just easier to use a look-up table.
I suppose I could use a UART, and send manchester encoded bytes using that..since the start and stop bit are zero-DC anyway (0-1) but I haven't seen any commercial standards that use this (like 802.xx, zigbee, keelog etc..). they simply send 'bits' usually bytes back-to-back.
I was hoping to find a microcontorller that can do this (and yes, I have checked the microcontroller forum, no-one answered) my only alternative is to do it entirely in software, which is hardly efficient, even on an ARM9.
Thanks again for the reply, its an odd question, and it seems that if anyone wants to design a wireless device for over 2MB/s and have complete control over the protocol, the only options are FPGA/CPLD and ASIC - both are expensive.
So, I will continue my search.
BuriedCode.
Ps, Just thought......using an external shiftregister, and using a micro's PWM to clock it...one would only load the SR once every 8-bits, and the clocking is done automatically......methinks I'll get my breadboard out...