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Bit sequence detector

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kingmaker

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sequence detector state transition diagram

Hi, I need to design a 0110/1001 sequence detector which produces a 1 output if the current input and the previous three inputs correspond to either the sequence 0110 or 1001. The output 1 is to occur at the time of the forth input of the recognized sequence.

Anyone can draw the state transition diagram? I'm not sure the correct answer. Thanks!
 

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State diagram sounds somewhat long-winded for that task. Just have a shift register and compare the output.
 

svicent

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I think the following diagram is valid if overlapping sequences is permitted
 

    kingmaker

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kingmaker

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svicent,
thanks for your working solution. by the way, could you please note down the state assignment for Q0 to Q6, easy for me to check the answer.
 

RBB

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This sounds like a homework problem. At least somebody else did your homework for you.
 

svicent

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kingmaker

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This button is viewable only for person who created topic and can be used only one per helpful message. This is a great way for thanks - only one click.

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kingmaker

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One question here,

is that any difference for the initial state for both Mealy and Moore machine if want to detect bit sequence 0110 ? Can direct set 0 to initial state?
 

svicent

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My opinion is: If you know the input initial value (the logic value before the first clock edge) you can choose the initial state:
If the input initial value is always 0, the initial state can be Q6 and Q0 can be eliminated.
If the input initial value is always 1, the initial state can be Q4 and Q0 can be eliminated.
If you don't know the input initial value you must keep Q0 as initial state
 

kingmaker

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I heard someone said that

for moore machine, we need initial state and for mealy machine, we can direct set the initial state as 0. is it true?
 

svicent

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For a proper operation, a state machine (Mealy or Moore) must enter a known initial state on power-up. In the above diagram, symbols Q0, Q1,...,Q6 are names of states that you must codify. Choose an initial coded state into which the state machine can easily be forced at reset, typically the state 000. If you choose Q6 as initial state, you must assign code 000 to state Q6. Most state machines have a reset signal, synchronous or asynchronous, that is asserted during power-up.
 

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