wonka
Newbie level 4
Hi,
Please help me in working out the project:
This is about Bit Error Ratio tester design for RF module.
The design require building sequencer and receiver in one CPLD (device:MAX7000).
The sequencer transfer bit stream to the RF module as input data, on the other hand, the receiver get the output data from RF module and checkout the bit error rate. Of course the design is working in bit synchronization.
Can anyone provide any useful references or give the method of realization of some techniques about this desgin?
Thank you very much!!
Please help me in working out the project:
This is about Bit Error Ratio tester design for RF module.
The design require building sequencer and receiver in one CPLD (device:MAX7000).
The sequencer transfer bit stream to the RF module as input data, on the other hand, the receiver get the output data from RF module and checkout the bit error rate. Of course the design is working in bit synchronization.
Can anyone provide any useful references or give the method of realization of some techniques about this desgin?
Thank you very much!!