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Bidirectional ports-Formality

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sam536

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In my Design, Bidirectional ports are creating problem in formal verification.
i tried to set set_direction as outputs in implementation and tried to verify and still verifcation is not passed at Ports.

Do we need to take care few things at bidirectional ports?. Do i need to set set_direction for both ref and implementation?.

how to take care of clock gating latches implemented with power compiler in implementation netlist. Can i add on all the latches as set_dont_verify ?.

your suggestions will be appreciated.

Regards,
Samba
 

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