The array is called twice at the module header, that seems to be the main problem..Error (10028): Can't resolve multiple constant drivers for net "<auto-generated>"
listfp LFP(
.invararr(valuearray[IDX]), [COLOR="#B22222"] "calling array"[/COLOR]
.vararr(valuearray[IDX])); [COLOR="#B22222"] "new array output"[/COLOR]
It seems like your problem has more to do with treating Verilog like a programming language, than describing a hardware logic design.
It looks like you are trying to use the array like a memory array in C than as a block of RAM or a bank of flip-flops.
The point I was making is you need to know how to draw a schematic of the logic design as Verilog for synthesis (Hardware Description Language) is not a programming language.
Well you seem to know more about how Verilog should be coded than I do, so there isn't any point repling to this thread.
Size limit for automatic for automatic RAM inference can be adjusted in synthesis options.
No chance to use block RAM in this case. This also means that array addresses and data bus are only virtual and not actually implemented in your design. Instead a large number of logic cells is needed to multiplex the data path.
See what the middle "goldylock" zone (whatever the heck that is supposed to mean) gets you, an impossible to implement design, because you didn't draw the circuit before you started coding. Even now if the design gets complicated enough I draw at the minimum a detailed block diagram and determine how the circuit works before I start coding and I've been writing VHDL/Verilog for ~3 decades.Well it's not more efficient in synthesis anyway, so I went for the middle "goldylocks" zone in ease of coding vs serialism.
FvM; said:No chance to use block RAM in this case. This also means that array addresses and data bus are only virtual and not actually implemented in your design. Instead a large number of logic cells is needed to multiplex the data path.
Exactly what I was trying to point out back in posts #4,6, & 8, but got shut down as
See what the middle "goldylock" zone (whatever the heck that is supposed to mean) gets you, an impossible to implement design, because you didn't draw the circuit before you started coding. Even now if the design gets complicated enough I draw at the minimum a detailed block diagram and determine how the circuit works before I start coding and I've been writing VHDL/Verilog for ~3 decades.
C like arrays are hard to synthesize in an FPGA unless they are specifically designed to be implemented in a RAM and yours wasn't. Yours would have to be done all in FFs and if the array is large it will take a long time to synthesize or may be impossible if it exceeds the number of FFs in the chosen part.
13% LEs of an A2 or A9 device?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?