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Biasing common gate with current mirror

Hawaslsh

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Hi all,

1620936564303.png
1620937621254.png

Relatively new to CMOS design so I had a pretty basic question. I am working on a common gate input stage to a amplifier. Above is the circuit schematic for the stage. I am trying to use current mirrors to set the drain current. From what I have read so far, it seems common practice to bias the PMOS current source with a current mirror to create an active load. But no examples I have read showed how to bias the gate properly. Is it bad to use a current mirror as well for the common gate biasing, or should I just use a resistive divider from Vdd? I got pretty good small signal results using this method. Id in this case was very close to Iref, as expected
1620937341427.png
1620937475752.png

I tried it with the resistors and get a very different response. Iref = 1.5m and Id in this case is 1.9mA The biggest difference is the output impedance, which I want to keep large.
 
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dick_freebird

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Common-gate wants the gate, you know, "common". That is,
zero driving impedance. Current source is high Z, resistor is
medium-Z. You would at least want an "AC short" (a good
and probably large shunt C to signal ground) and a high-Z
DC bias (high enough that the RC corner is above frequencies
of interest). But another interest may be linearity, and then
simple thin film resistors (large value) might be better as
they lack the drain junction nonlinear capacitance of a
current source FET.
 

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