Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Beta in STD CELLS, Process cornors

Status
Not open for further replies.

Prashanthanilm

Full Member level 5
Joined
Aug 24, 2012
Messages
303
Helped
36
Reputation
72
Reaction score
36
Trophy points
1,308
Activity points
2,950
Hi All,

We calculate beta value for the cell library by calculating the average delay for the basic gates and boolean function. We run these simualation in FF and SS corners. Ie the best and the worst case.

Can anyone please elaborate the importance of running the simulation in TT corner?

Thank you,
Prashanth
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top