reg [(8 * `NUMBEROFENTRIES) - 1:0] Registers;
I think the last-write-wins is in terms of having multiple reachable assignments in the same clock edge of a process. It would be a short way to write the logic. It implies muxes for the input to each register, which might be acceptable but would be more LUTs than a shared scheme. The LUTs are likely near the registers anyways though.
This method would work, but would again require some kind of signal to each module indicating when data can be written.Can´t you multiplex the register access in the time?
Using three cycles could do the job.
Cycle1: Write/Read A
Cycle2: Write/Read B
Cycle3: Write/Read External
Can´t you multiplex the register access in the time?
Using three cycles could do the job.
Cycle1: Write/Read A
Cycle2: Write/Read B
Cycle3: Write/Read External
Using a mux is not the same as 'following' the last write with another write. That implies queuing writes with a fifo or some other kind of storage mechanism.
// this is a mux.
always@(posedge clk) begin
value <= external_data; // so always do the external non-blocking write first
if (merged_write) begin // followed by the merged A/B write
value <= merged_data; // the "last write wins" approach
end
end
Registers[Address_1 * 8 +: 8] <= (Registers[Address_1 * 8 +: 8] & MaskIn_1) | DataIn_1;
// writing - port 0
if (Write_0) begin
if (Address_0 < `REG_NUMBEROFREGISTERS) begin
Registers[Address_0 * 8 +: 8] <= DataIn_0 & WriteMasks[Address_0 * 8 +: 8];
end
end
// if writing on ports 1 and 2 at the same time and with the same address
if (Write_1 && Write_2 && (Address_1 == Address_2)) begin
if (Address_1 < `REG_NUMBEROFREGISTERS) begin
Registers[Address_1 * 8 +: 8] <= (((Registers[Address_1 * 8 +: 8] & MaskIn_1) | DataIn_1) & MaskIn_2) | DataIn_2;
end
end else begin
// writing - port 1
if (Write_1) begin
if (Address_1 < `REG_NUMBEROFREGISTERS) begin
Registers[Address_1 * 8 +: 8] <= (Registers[Address_1 * 8 +: 8] & MaskIn_1) | DataIn_1;
end
// writing - port 2
end else if (Write_2) begin
if (Address_2 < `REG_NUMBEROFREGISTERS) begin
Registers[Address_2 * 8 +: 8] <= (Registers[Address_2 * 8 +: 8] & MaskIn_2) | DataIn_2;
end
end
end
You should really learn how to use parameters instead of `define. defines are really annoying and not very portable and can make reuse impossible.
`define REG_ADDRESS_TXBUSY 4'h4
`define REG_BITNUM_TXBUSY 8'b00000100
`define REG_ADDRESS_COUNTERS 4'h5
`define REG_MASK_ERRORCOUNTER 8'b00001111
`define REG_MASK_TXCOUNTER 8'b11110000
`define REG_NUMBEROFREGISTERS 8
Are you sure the both A and B need to WRITE bit two of this register?Suppose I have a peripheral register at address 0x04 and in that register bit two is called "TXBUSY". I need to read/write this bit from modules A and B.
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