best # of inputs for logic gate

[oermens]

i remember reading on this forum (not sure which board) that the optimum number of inputs for a digital circuit is 3 or 4, and that is used to synthesize larger circuits. can someone please provide me with paper explaining why this is. thanks.

 

[carv_13]

These links might help you a bit. Generally we try to minimize the delay in circuits. With increase in number of inputs, you would have to increase the size of PMOS and NMOS devices to get a good performance in terms of delay. But there is a point beyond which increasing the size does not lead to improvement in delay and will lead to infact slower circuits. This is because with increase in size, the internal capacitance becomes a very crucial factor and self loading of circuits takes place leading to slower circuits. There was paper which dealt with this but I can't find it out as of now.

**broken link removed**
**broken link removed**

 

[onlymusic16]

Hi,

Carv is right! On increasing W of a p or n type device to speed up the circuitry, you increase the gate cap also. No doubt the current driving capability of the device increases but the inherent gate cap also increases, which at one point of time, slows down the circuitry (instead of speeding it up).

 

[master_picengineer]

In fact this is a consequence of the shrinking feature size. New physical undesired factors reduce performance of the devices in particumar, delays, crostal, power consumption. The optimum is to use serial interconnects.

 

[oermens]

thanks but is there any paper which explicitly proves where the # of gates and delay/power tradeoff is optimized? f. ex. if i want NAND8 why is it better to use 2x NAND4 and NAND2 than 1x NAND8? i'm just too lazy to do the math myself, its for an assignment i'm doing and if someone has already formalized this proof i'd rather just refer to it than reprove it.

 

[master_picengineer]

logical effort
google it and you'll find what you need.

In addition here is a nice book:
Designing Fast CMOS Circuits - logical effort

 

[carv_13]

Yep. Logical effort will prove that its better to use NAND 4 to build a NAND 8 gate than use one single NAND 8 gate. I think you can get the formulae in the links that I have provided.

 

[gliss]

Yes, the rule of thumb max is usually 4 for most processes.

 

[carv_13]

I think there is actually a paper that deals with this topic and also tells how the magical number of 4 was found out. Would be great to read that paper if someone can find it and post it.

 

[onlymusic16]

Yes, the magical number 4 is indeed a realistic number. I have been searching for that paper, still not able to get it. It will be great to read that paper. Anyone who finds it, please upload it here.