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# Best Methodology for Devices Sizing

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#### MohamedA

##### Newbie
Hi All,

I finished many courses in Analog IC design, but since most of them are assuming square law model which is not valid in newer technology nodes i find myself stuck on how can i really size the devices, how can i choose the proper W/L of the devices based on a certain spec without being a spice monkey.
Is the gm/id the best solution? Is that enough? Do we have different sizing methodologies rather than gm/id?

I would be glad if you can answer my question.

Thanks,
MohamedA

#### dick_freebird

##### Advanced Member level 5
Since transistor operation doesn't have a valid closed
form expression (have you looked at the parameter-
count, for advanced models? Or considered that none
of them are anymore "analytical", but empirical?)
maybe you should just pack a banana for lunch.

Square law model isn't really useful for modern
CMOS analog design, which mostly wants to be
in subthreshold (log-linear, not square law) for
low bandwidth DC amps - which for predictable
reasons tend to suck, on sub-250nm flows. At
VT you're not really in either regime, so you've
got nothing for valid device equations to solve.

Everybody's got to find the methods that work
for them. Gut plus SPICE works for me. I can run
a dozen alternatives in the time it'd take me to
hand-solve one geometry-set's equations and
pick the one that moves me toward the goal.
Even if I got the equations right.

It does behoove you to verify that the models you
are given to use, produce sensible results for real
transistors' I-V curves, but generally foundry
modeling folks have done that and prepared the
documents.

In that case, what value do you imagine you add
by doing it with primitive methods? You're
working with a pencil, and you call SPICE users the
monkeys? That's like a caveman laughing at the
guy with the jackhammer, because he's got a
real sweet club.

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