Best FPGA for high speed ADC read/transfer

[oliglaser]

Hi all,

I am designing a reasonably priced, medium speed (up to 300Msps hopefully) USB scope.
I have plenty of experience with MCUs, firmware, PC software etc etc, but have only just got into FPGAs - I have just etched my own basic test board with an Actel ProASIC3 device which is working fine, just to have a mess about and get up to speed with stuff.
The next step is designing a high speed multilayer board to read the ADC and implement the triggering an so on. I am looking for the best device (preferably Actel as I have the Flash Pro4 programmer now but any device considered - I know there are other faster chips out there)
Ideally the chip would have on board flash configuration (one reason I chose the ProASIC3) and have enough on board RAM to store around a million 8-bit samples so I don't have to worry about external RAM addressing and the high speed transfer.
Obviously it's likely I will have to compromise somewhere here so am willing to do so and consider any advice or suggestions people may have, especially as I want to keep the final sale price low.
Any help would be much appreciated, thank you.

On a side note - I would like to grab a USB JTAG programmer that does most of the main FPGA vendors (Xilinx, Altera) and is compatible with the IDEs and well documented - any advice here would be good too.

 

[permute]

I'm not sure how many lower-cost FPGAs will store 1MB. I suggest using a commodity DDR chip for this type of application. Most vendors have free IP or even hard-IP for this. With modern ICs, you can get well over 1MB in a single DDR2/3 IC. Of course there are more costly FPGAs that will have enough SRAM for 1MSamples.

I suggest DDR over QDR or on-chip SRAM, as DDR2/3 both have on-die termination, making signal integrity easy. Further, if you use 16b IO, you can run the interface at 166-250MHZ (or whatever the minimum DLL lock rate is), and even 2T timing, making interfacing simple. (if you do this for Xilinx, look into using SSTL class 1. SSTL class 2's implementation uses more power...)

In the end, the DDR route might be smaller, as some FPGAs that have the required SRAM also need bigger packages.

this should allow you to use lower cost FPGAs, commodity SDRAM, and whatever USB Phy you want. All while wildly exceeding the 1MB spec.\

for programming, you may end up using a low cost micro that can program the FPGA over USB. or you might use the built in program from commodity EEPROM feature of modern FPGAs. Its your choice.

 

[oliglaser]

Thanks for the reply, I will consider the DDR with external RAM and look into it, as it was my initial plan in any case, I just had a thought looking at some of the Xilinx chips with the larger on board RAM that there may be another way. To be honest, using external RAM is probably the way as storing far more than 1 Megasamples would be good, as even that gives hardly any storage at high sampling rates.

Any recommendations for the chip? Does anyone know who makes the fastest FPGAs for this kind of thing? I don't need much complexity logic wise, just raw speed really.
The logic will just be something like a digital comparator, address generator and multiplexer, with some trigger algorithms. Getting up to >500MHz would be nice at some point, although that would be a different project.

With the programming, is the Amontec USB JTAGKey any good? Or would getting the vendors programmer be better? (debugging etc?)
With the EEPROM you mention - how does this work - you just program the eeprom and it uploads the config at power up? Can you reprogram in circuit for prototyping purposes with this method?
Ideally the in circuit programming is what I want like with the FlashPro4, as I can make the board and then try various ideas out by reprogramming the device. I'm pretty new to the FPGA world so the ways of doing stuff like this is not totally obvious to me...

 

[Sink0]

I am kind new to FPGA too so i cant give some advice about the device but take a look at these links:

**broken link removed**

**broken link removed**

Respectively clones for ALtera and Xilinx USB download cables. I got the Altera one. It works very well with cyclone II. Even the Jtag Logic Analizer is flawless. I am not sure about high end devices but the vendor told me it should works with all devices that the original one does. Actualy the vendor is very trustful. I strongly recomend him.

 

[oliglaser]

Thanks very much, they look very good. Will help save a few quid..

 

[lucbra]

There are a couple of other things you will need to consider as well:

The front end ADC will have a high speed parallel -ish interface (maybe even LVDS). The FPGA will need to be able to handle these signals, route these to a buffer memory and psuhing it out.

Because you want to store 1Msamples (8bit), you will need 8Mbit of memory inside the FPGA. This is not possible for low cost devices. I would try to implement this in an external DDR2 RAM.

I see you are based in the UK. If you stuck with Actel (because of the flash technology) then you will need to talk to an Actel FAE (pls PM me for his name). Other options are to work with an SRAM FPGA: here are the options CycloneIV, Spartan6, ECP3. All should be fast enough to handle the signals, and have dedicated I/F to DDR2/3.

Best regards,