bessel filter as a differetiator question

[yefj]

Hello, A circuit below presents bessel filter which is acting as differentiator .
few question:
1. How the denominator of a transfer function is defining the group delay?
2.given the configuration below how did they know to choose the following opamp configuration to implement the transfer function?
3.My pluses are smeered ,how do I make them sharper?
Ltspice file is attached.
Thanks.

 

[yefj]

Hello,I have rising edge of 1n and falling edge of 1n second these edges are separates by 2usec at the input as shown below, the filter I built roughly does differntiation a little.
Turning a pulse into two spikes.

I want sharp peaks with the same amplitude.
What group delay should I use for this case?

 

[LvW]

Hello,I have rising edge of 1n and falling edge of 1n second these edges are separates by 2usec at the input as shown below, the filter I built roughly does differntiation a little.
Turning a pulse into two spikes.

I want sharp peaks with the same amplitude.
What group delay should I use for this case?

Why do you think that the group delay plays an important role for the differentiating process?
What you need is a constant rising phase shift in the frequency range of interest (similar tot a 1st-order highpass), thats all.
Your circuit can provide this up to app. 10 kHz.
This can also be achieved with a simple highpass consisting of R1, C1 and R2 (setting C2=C3=R3=0)

 

[FvM]

The filter can be better anaylyzed as cascaded first order high pass (performing the differentation) and a second order low pass of Bessel type. Output pulse width is set by low pass cut-off frequency. Pulse form will be always a kind of smooth pulse, that's obviously the objective of the "differentiator" design you have used.

A sharp rising, exponential falling pulse can be produced by a simple high pass

--- Updated Mar 9, 2025 ---

It's not possible to make a rectangular pulse with lumped filters, you can either use transmission lines as pulse formers or a non-linear analog circuit.

 

[LvW]

What you need is a constant rising phase shift in the frequency range of interest (similar tot a 1st-order highpass), thats all.
Your circuit can provide this up to app. 10 kHz.
This can also be achieved with a simple highpass consisting of R1, C1 and R2 (setting C2=C3=R3=0)

Sorry for the 1st line - it is wrong!
You need a rising gain response and a fixed phase shift of 90 deg.

 

[FvM]

I think we are missing a specification of intended output waveform. "Differentiator" doesn't seem to describe it appropriately.

 

[D.A.(Tony)Stewart]

Let's try a more logical approach: ( High speed Analog)

Using high speed current mode logic CML or LVDS Buffer.

Design Spec:

• Use a differential delay line approach to create a square pulse on each edge. (aka frequency double, edge detector)
• Input: 10 MHz clock Tr<= 1ns , any duty factor as long as PW50 > delay line time, Td
• Choose any delay line = 1 ~ 2 ns using all-pass matched microstrip, semi-rigid coax or COTS delay line
• Use RF driver with low C out~ 1~2pF and 10 GHz BW. Choose any impedance e.g 50 , 75 100 Ohms for your circuit.

Consider the best choice for accuracy and stability for an edge pulse detector (1-shot, dV/dt, LVDS. , XOR gate ) e.g.

1. DS90LV001 800 Mbps LVDS Buffer or equiv
2. CML XOR gate or an HMC721LC3C or MC10EP08, MC100EP08 or equiv.

Simulate to achieve a pw50= Td +/-10% for 3.3 V logic levels after each input transition prop delay = < 2 ns and stable within 1% at a controlled lab temperature.

Amplitude with SNR >10 to guarantee stable logic level out.

You will use real sources.
I simulated a 1ns rise time using an ideal 0 ohm voltage source and ideal parts as shown using a common base. You can use a microwave Clock Buffer or LVDS driver or CML logic or ECL.

Good luck with your Sim and layout. Feel free to revise any specs but document it.

 

[D.A.(Tony)Stewart]

A linear amp yields a bipolar pulse but these are hard to realize.