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ICs can be expected to get damaged if exceeding the absolute maximum ratings. To achieve the specified peformance, you are required to keep the recommended operation conditions, e.g. Vcc = 5V +/- 5% for classical TTL and LSTTL devices.
TTL logic isn't designed to operate over a wider voltage range, HCMOS (74HC familiy) in contrast is. It has voltage dependent speed according to variation of MOSFET Rdson over gate voltage.
It's unlikely to damage logic ICs by a too low supply voltage.
Yes when I lower the +VCC below 5 volts around 4 volts dc, it will cause the TTL logic chips to get really hot and the propagation delay gets slower or longer. Any reasons why this happens?
TTL has transistors, when lowering the voltage on transistors it doesn't damage them or get them hot. So why does TTL chips get hot and get damaged.
The gain of transistors may vary in function of the biasing current. The electric characteristic of inner components certainly are optimized to meets the optimal performance at the recommended operation conditions far from linear region.
I doubt that TTL logic gets hot or will be even damaged at 4 V as a general case. That's probably a specific problem of your test setup. Can you describe the circuit in detail?
Slower operation is however expectable. Transistor current are reduced and capcitances maintained. Results typically in slower switching. You are operating the devices outside the specified voltage range and can't be sure to get meaningful output signals at all.
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