Behavioral verilog-A model for sigma-delta modulator

[samvelc]

sigma delta verilog

Hi all,

I'm looking for a behavioral verilog-A or verilog-AMS model for sigma-delta modulator.

Thanks in advance.

 

[qslazio]

sigma delta modulator verilog

a simple example:
http://www.eda.org/verilog-ams/htmlpages/sample_lib.adcm.html#Analog/DigitalConverter

 

[samvelc]

behavioral modeling of sigma-delta modulators

a simple example:
http://www.eda.org/verilog-ams/htmlpages/sample_lib.adcm.html#Analog/DigitalConverter

Thank you,
But I have already seen this site.
It is not so good example