Behavioral modelling for analog designs

[chviswanadh]

behavioral modelling in cadence

Hello,

Can anybody tell me how these behavioral models of analog designs come into use for the verification of the Mixed signal design.

And also the languages used for the modelling

Thanks
Kasi

 

[pixel]

behavioral view cadence

In Cadence you can use ahdl and verlioga for behavioral analog modeling.
**broken link removed**

 

[pfd001]

matlab can also be use for behav model

 

[ynhe]

SImetrix is good for Behavioral modelling for analog designs.

 

[adefan]

VHDL-AMS or Verilog-A

 

[shaikhsarfraz]

Hi
When we are designing a complex chip. The chip might contain some critical stages.
It is not judicial to complete the design of the whole block and than verify the chip as a whole as failure at that time will be devastating.
Instead we design the critical blocks and we write the behavioural model for other blocks which meets the specification, and the whole block is integrated and verification can be done along side design process. Any fault in the design can be rectified at that stage only.

We can use either
Verilog A or Verilog AMS for behavioural modelling.
Remember Verilog A cannt be used to model digital blocks.
These codes can be simulated using cadence Spectre.

 

[aibrahim]

For system like delta sigma ADC the simulation of the whole system in circuit level directly will consume many days so we need to first to design a simple behavirol model for entire delta sigma ADC before map this case to circuit level to minimize the time consumed for your design.
you can do this using Matlab or verilog-a , verilog-AMs and both also subitted in cadence ,ADS tool also available.
for example for delta sigma ADc the most available tools in matlab
for PLL design you can find verilog models and matlab ones also.