Re: Beginner question re. behaviour of synthesised VHDL and propagation delay of proc
What you have to understand here is that VHDL is a bahavioural langauge, and synthesised VHDL is a circuit. In your example, your code could "work" just fine as VHDL works on a set of rules, but the synthesised circuit is likely to behave in all sorts of ways because of factors outside of your control in VHDL.
The following statements that sig_in comes from an asynchronous source. If sig_in is already synchronous to the same clk as the 2nd process, then there is no problem.
Because the second process is synchronous - you know when sig_out will be sampled - on the rising edge of the clock.
VHDL works by using delta cycles - infinitely small increments in time. Any event can only occur in a single delta cycle. In the following code, you know the assignments will work, because each assignment triggers the assignment to occur in the next delta cycle:
While on a waveform they would all appear to transition at the same time, they actually all have a delta cycle delay (this can cause some gatchas in VHDL).
VHDL knows nothing about internal delays, pin IOs, track delays, temperature - and it does not care. You may want to model these in your VHDL with "after" delays, but these are ignored for synthesis because they were just that - a model. The synthesisor has to make a real circuit. It is then down to the user to know the IO delays required and input them to the project via the SDC file.
You need to understand your VHDL will become a circuit when synthesised. And you need to know how that circuit should behave. It is very possible to write VHDL that works one way in a simulator, and another way on hardware.
So no - there is no "magic" that VHDL does to "make things work". As with any code, it just follows the rules of the language and does exactly what you wrote in the code.