Beginner problem : help me to synchronize an ADC signal DATA with the FPGA clock

[houly]

Hello all,
Thanks for your replies... FvM, I don't use DCO since I would want to minimize the line beetwen the analog board (with ADC) and the digital board (which receive only DATA form my 8 ADCs), so I don't need the DCO which is the echoed clock from ADC.

What is a FF controller ?

If I understand well, SERDES and recovery features can't be compatible with the stream from the ADC (header + 16 bits of data), or do I miss something... ?

I have to make a choice of architecture now, so what could be the conclusion for the clock source of the ADC ? and does the clock recovery system proposed by Analog Device could be used ?

Another question : The space between the digital board and the analog one is about 5cm, what sort of connector and cable could be fine to transfer LVDS lines ?

Thanks a lot for your help

 

[dave9000]

What is a FF controller ?

That was "an external FF controlled by the FPGA".
For example you may use a D flip-flop clocked by a low-jitter 40MHz source. The input would be a 25% duty-cycle 10MHz signal generated by the FPGA (from the same clock), so that you can meet the Tcnvh requirement of the ADC.

 

[FvM]

The FF discussion was about achieving a low jitter start of conversion signal, but you didn't tell about your jitter requierements, in so far it's a purely theoretical discussion up to now.

The other point is the decoding of serialized data. I see two options with Arria FPGA:
- Using SERDES in logic cells, driven by DCO, no receiver PLL. A simple, straightforward method.
- Using Arria dedicated hardware SERDES, which is always driven by a PLL. Arria can do this with a single PLL for 8 ADCs, if the internal clock is used rather than DCO. DPA functionality with the specific ADC frame must be checked, I guess, it can still work.

For the connector, any standard with an differential impedance around 100 ohm can work. For short distance even a standard 0.1" pin header with IDC cable.