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What details are required here?.I need to design a uart with baud rate 2400.My FPGA clock is 100MHz.so how should i calculate the value in order to get baudrate 2400.
I hope I am clear now.
Most UART´s need a clock at 16 times the baud rate.
In this case 2400*16 = 38400 Hz
To generate this you should divide 100 MHz by (100M / 38400) = 2604.16666...
The error you get by rounding this to the nearest integer is small.
Dividing by 2604 will give you the baudrate 2400.15
That is OK.
A baudrate difference between transmitter and receiver of up to about 1-2% is probably OK.
In some situations with a slower clock and higher baudrate it can be impossible to find an integer divisor which is close enough. You can then use a fractional divider which will give jitter on the transmitted data, but that is normally acceptable.
If you design your own UART you can have the clock different from 16 times the baudrate. It is the receiver that needs a clock higher than the baudrate.The minimum clock frequency is 3 times the baudrate. The transmitter can have a clock frequency identical to the baud rate.
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