I didn't look at your code earlier, but now that I have you've got lots of typo problems and you've got to learn Verilog 2001 instead of using antiquated coding of the module ports that can result in more typing and errors like you have.
e.g.
module spimaster (clk, cs, spiclk, datain, dataoutpin);
is not the same set of signals...
input clk, datain;
output cs, spiclk, doutp;
dataoutpin is not going to be connected to doutp.
You are also not using the conventional SPI signal names...
SCLK, CS_N, MOSI, and MISO for the ports of the module. You also named MISO as moso (master out slave out!)
You are missing any kind of shifting of the MOSI and MISO to the output and input respectively.
I'm not even going to attempt to analyze any more of the code as this isn't even close to functional.