[SOLVED] Basic Serializer Verilog

[stark43]

Hello everyone. I'm new to Verilog. I want to convert a parallel data to serial, but without success. What are the bullshit and flaws in my code?

----- TOP------------------
`timescale 1ns / 1ps

module Serializer(
    input  wire clk,
    input  wire [7:0] in_data,
    input  wire valid_data,
    output reg out_data
    );
     
    reg [7:0] temp_data;

    always @(posedge clk)
    begin
    temp_data <= in_data;
        if(valid_data == 1)
        begin
            temp_data <= {1'b0, temp_data[7:1]};
            out_data <= temp_data[0];

        end
     
    end
 
 
endmodule





-----TESTBENCH-------------
`timescale 1ns / 1ps

module tb_serializer();

reg tb_clk = 1'b0;        
reg [7:0] tb_in_data = 8'b01010011;
reg tb_valid_data =1'b1;
wire tb_out_data ;  

//Clock
always begin
tb_clk = ~tb_clk;
#5;
end

//Testbench Connection
Serializer DUT(        
    .clk(tb_clk),      
    .in_data(tb_in_data),
    .valid_data(tb_valid_data),
    .out_data(tb_out_data)
);                  

//Serializer

initial begin
#200;
tb_in_data = 8'b11001111;
end


 
endmodule

 

[dpaul]

What are the bullshit and flaws in my code?

The simulation waveform should indicate the bull**** happening!

1. The bits should be shifted out serially on every rising edge of the clock, where are you doing it?
2. valid_data is not being driven in the TB
3. Search "parallel to serial data conversion + Verilog"

 

[ads-ee]

---

Code Verilog - [expand]
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always @(posedge clk)
    begin
        temp_data <= in_data;     //<<<<< this is done in parallel with the if statement below
        if(valid_data == 1)
        begin
            temp_data <= {1'b0, temp_data[7:1]};  //<<<<< simulator always does this as valid_data is always 1
            out_data <= temp_data[0];
        end
    end

---

Since the two statements commented above are always done at the posedge of the clock the result is only the if statement assignment is effectively completed.

You need a separate load signal or use the inactive state of valid, i.e. !valid_data, to perform the temp_data <= in_data; assignment.

---

Code Verilog - [expand]
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always @(posedge clk)
    begin
        if (!valid_data) begin    // load in_data into temp_data when valid_data == 0
            temp_data <= in_data;
        end
        else if (valid_data == 1)      // enables the shift register
        begin
            temp_data <= {1'b0, temp_data[7:1]};
            out_data <= temp_data[0];
        end
    end

---

I would rename the signals to reflect what they are actually doing:
valid_data >>> shift_loadn
temp_data >>> shift_reg
out_data >>> serial_out