Basic rules for planning the power routing of a design

[kjtom]

I am a newer for APR.
There is a technical and empirical step, badgering me.

How wide of power line? How many straps line needed?....
Are there some "basic rules for planning the power routing of design" ?

Could any predecessor give me guides or document? Thanks

 

[sree205]

About power routing?

not sure of APR. there is a document called "dtmf" from encounter, available in this forum. it gives a brief overview of how the power rings and stripes are used in a sample design. if u go through it, u might get a basic idea.

 

[jackson_peng]

About power routing?

Generally, EM and IRdrop is considered in the power plan.

EM confine the max electricity on the metal and via, which you can find in your techonology library, .lef(Cadence), .tf(Synopsys).

IR drop confine the max voltage drop in the chip area, which you can find some clue in the cell timing library, .tlf (cadence) and .lib (synopsys). generally, the worst drop should be limited below 10%.

tools are available for analysis of the EM and IRdrop, and your job is simply draw a acceptable power network in regarding the above two factor.

however, it's not quite simple as it sounds.

have fun.

 

[nav_vlsi]

Re: About power routing?

In order size power strap width , there is a method given in site www.vlsi-technology.org , there will be paper on IR drop or just refer the pdf given( i have just grouped all html pages of that paper and converted into pdf).

pitch , width and group spacing is important mesh design.

just read that pdf and incase of any query do get back to me

regards
navien

 

[armmips]

Re: About power routing?

It is very useful. Thanks for your sharing.

 

[hiral.kotak]

Re: About power routing?

Hi,

Pls refer the link:
https://asic-soc.blogspot.com/2007/10/power-planning.html

It may help you.

Thanks..

HAK..

 

[sreevyas]

Re: About power routing?

navien,
great compilation, it usefull

__sree