Basic questions about synthesis process

[phoenix_pavan]

What are the two most fundamental inputs (files) to the synthesis tool?

What are two important steps in synthesis? What happens in those steps?

What are the two major output (files) from the synthesis process?

 

[RBB]

Re: synthesis question

What are the two most fundamental inputs (files) to the synthesis tool?

I would say input netlist and libraries.

What are two important steps in synthesis? What happens in those steps?

Elaboration: Mapping the hdl into generic cells. Compilation: Compiling the generic cells into library specific cells.

What are the two major output (files) from the synthesis process?

Output netlist and I'd say timing reports.

 

[sree205]

synthesis question

one more output file is an SDF file, which is used in prelayout dynamic timing simulations

 

[aravind]

synthesis question

INSTEAD SDF .. SDC is must friend

 

[risccpu]

synthesis question

the two major output (files) from the synthesis process: netlist and sdc.

 

[ljxpjpjljx]

Re: synthesis question

output file is netlist,sdc,sdf!

 

[chipking005]

synthesis question

For Synthesis,

I/P files : RTL,Library files(like IOPADS,Technology supporting files) ----> SDC

O/P files : Netlist and SDF

 

[nine8]

synthesis question

input: RTL , constraint and tech database

step: translation + logic optimizaiton + gate mapping

output: netlist + .ddc + sdf +sdc