Basic questions about gate level net list

[pravi]

Gate level net list

1.What is gate level net list.
2.what are the inputs and outputs a gate level netlist
3.is the generated netlist will have any timing .
4.or how it is different from RTL.
5.any good example or link site

 

[tarkyss]

Gate level net list

gate level netlist is composed of cells in the synthesis library,
the function of synthesis is mapping your RTL design to a technology, the result of synthesis is gate level netlist,
so the function of the gate level netlist is the same with the rtl netlist, the port too.

 

[pravi]

Re: Gate level net list

so what about the timing ..will there be any timing comes into picture in gate level net list..so if we are giving inputs to a accelerator what is the input

 

[naveen reddy]

Re: Gate level net list

1.Gate level netlist is the representation of a circuit in terms of its gates and there interconnections between them.

2.no the generated net list will not have any timming

3.RTL is technology independent where as netlist is technology dependent

 

[deva_eda]

Gate level net list

naveen reddy,

Gate netlist is composed of technolog cells, so what about the timing arcs information available in these cells.

I guess the timing information is available in at the gate level. Though this timing information is not exactly is same after cts and p&R

 

[omara007]

Re: Gate level net list

The timing or what we can call Delay has 2 sources :
1- component delay
2- interconnect delay

component delay can be contained in the netlist as there are all the cell components, while the interconnect delay won't be clear unless physical synthesis and P&R .. there is something deserves mentioning which is Wire load model for interconnects .. yet, it's not the same as real interconnects

 

[anan_tv]

Re: Gate level net list

Haiii reddy,

I have gone thru ur replies so far.

If the Interconnect delay is not so accurate in the gate level netlist (technology dependent), then how the accuracy of the Component delay ???

If a technology mapping happens, then definitely the delays incurred would be defined.

So I think both the delays would be defined upto some extent.

Hope to get more details on the same.

thankyou

 

[omara007]

Re: Gate level net list

If the Interconnect delay is not so accurate in the gate level netlist (technology dependent), then how the accuracy of the Component delay ???

If a technology mapping happens, then definitely the delays incurred would be defined.

So I think both the delays would be defined upto some extent. thankyou

interconnects depend on the design itself .. for example :
if you have put 2 blocks 10 mm apart from each others on the die .. the interconnect between the ports will be 10 mm .. while if u put them 5 mm apart, it will be 5 mm ..
you are forced with ur design size and nature to put things relative to each others with variable placing nature .. this is called ( Floow Planning ) of the design ..

according to that, you can't predict exactly the length of the interconnects after synthesis .. cuz u need first to go for Place and Rounte ..

is this clear ?

 

[smith_kang]

Re: Gate level net list

Gate level netlist is the outcome of Synthesis tool which translate RTL in to Technology dependent netlist.The functionality of the design remain same.It is just a tranlated form of RTL.
Timimg as omara007 said composed of component delay and interconnect delay.For Interconnect delay WLM were used but now slowly this practice is being discouraged and instread Custom WLM which are generated after P&R are used.
Also the term Logical Synthesis is giving way to Physical Synthesis.

 

[anjali]

Re: Gate level net list

as far as i know gate level netlist in db format can store the timing info regarding the timing constraints.

 

[senthilvadivu]

Re: Gate level net list

**broken link removed**

 

[anan_tv]

Re: Gate level net list

Haii omara,

thanks for the detailed explaination on delays.

But as SMITH said , if the logical synthesis is giving way to physical synthesis, then we can get the timing information even after "synthesis" in the netlist itself?????

 

[miho]

Re: Gate level net list

@anan_tv: Physical synthesis means that the compiler that translates from RTL to netlist takes physical effects into better account than just WLM. Essentially they run a trial P&R in the background. Then they estimate delay from that instead of just the WLM.

PS: If there is timing depends on the format of the netlist. often it is plain verilog. then you need to annotate the timing during elaboration from an sdf file that the timing extractor generated from the parasitics (e.g. SPEF) file.

 

[anan_tv]

Re: Gate level net list

Haii miho,

@anan_tv: Physical synthesis means that the compiler that translates from RTL to netlist takes physical effects into better account than just WLM. Essentially they run a trial P&R in the background. Then they estimate delay from that instead of just the WLM.

If this is the case , we can get timing details from the physical synthesis unlike logical synthesis.

how far that results reflect the final stage timing closure???

how does the SPEF file generated???[/code]

 

[kermit]

Re: Gate level net list

anan_tv

If this is the case , we can get timing details from the physical synthesis unlike logical synthesis.

how far that results reflect the final stage timing closure???

how does the SPEF file generated???

Yes, after physical sysnthesis the timing is more accuracy than one from logical synthesis.

After P&R, it generates timing information is the most accruracy. If you design meets the timing, you can say timing closure.

SPEF files can be gerenated by tools such as Fire & ICE (from cadence).

 

[liujingshu]

Re: Gate level net list

You can use the sdf file to back annotate the gate netlist. There will be timing

 

[kermit]

Re: Gate level net list

anan_tv:
STA tools such as PrimeTime and Pearl can read SPEF file,calcute the timing, write out sdf file.

 

[beckchm]

Re: Gate level net list

gate level net list is generated by synthesis tools

It comprises of the cell

 

[Nandy]

Re: Gate level net list

GOF, Gates-On-the-Fly is a graphical netlist Debug/ECO tool which is very helpful in processing verilog logic netlist. Goto www.nandigits.com and have a try. It's free.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.