Basic question in analog design

[analog_prodigy]

Hi friends,

Please clarify my doubt

1. usually while designing analog blocks, we choose L (length) values 2-5 times the minimum lenght. Why?

As L increases, the output resistance increases. That leads to high gain (gm * ro). Is it the reason for that? Or any other fabrication issue?


2. But, for digital blocks, i observed using the minimum length instead of multiplied. How can we use a minimum length for digital blocks while using 2-5 times L for analog blocks?

Thank you

 

[master_picengineer]

Hi,
1- Coz Mobility of electron in the NMOS is between 2 and 5 times than the mobility of the holes in the PMOS.

2 -Please elaborate.

 

[demair]

1- like your answer, this make the lambda of the mos low
2.-different (w/l) mos device used in analog and digital circuit showes the different application of analog and digital circuit

 

[gaom9]

I think it is to decrease the short channel effect. As the min channel is 0.18um, then if we choose the channel length as 2-3 times of it, the short channel effect will be low.
Also it is to make the circuit match better when it is in long channel.

Best regards!

 

[drming]

You can find the detail analysis of L for MOS at Ch1 and Ch2 of the following book:

Analog Design Essentials
Author: Willy M.C. Sansen

The books is available at:

**broken link removed**

 

[firry]

In the analog block, the large L can decrease the effect of lambda to current. It also can decrease mismatch of current mirro. In the degital block, since the mosfets are all switch, using minimum length to decrease die size.

 

[qqic]

for matching

 

[kwkam]

In analog design, matching is more important than gm. Therefore, make the MOS length and width at least 2~3 time from the minimum.

 

[gpwu]

Longer L will have less channel length modulaiton, therefore, higher gain which is important for analog circuit.
Digital circuit need less delay, so minimum L&W is important for speed and lower power.

 

[drming]

You can find the detail analysis of L for MOS at Ch1 and Ch2 of the following book:

Analog Design Essentials
Author: Willy M.C. Sansen

The books is available at:

**broken link removed**

I found out the link has been moved to:

**broken link removed**

 

[amandeep_pec]

I think its because of the increase in the output resistance...

 

[suria3]

For differential amplifiers, larger L at tail transistor will make higher CMRR at higher frequencies.

 

[analog_prodigy]

HI friends,

Thanks to all for your valuable comments.

From baker book i found that

output resistance(and hence gain) is proportional to ( (L*L) / (Vdsat * Vdsat) )

transition frequency (speed of the device) is proportional to ( (Vdsat) / (L*L) )


To achieve a good compromise between gain and speed, we usually choose L = 2-5 times the minimum length for analog design.

For digital circuits, speed is the ultimate goal compared to gain, which is inversely proportional to (L*L). So, we use the minimum length for digital circuits.

I found this information from baker text book.

ONce again thanks to all for sharing the concepts.